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Honored Contributor
Honored ContributorTrouble loading User design to FPGA
Hi, preface: I currently have a design that runs great on a NiosII CycloneII Dev Board. I am trying to port my design over to the NiosII StratixII Dev Board, but was running into problems (th...
Altera_ForumHonored Contributor
Honored ContributorI know that dev. board has a MAX device that loads the configuration from flash. Is that defeating your load? Maybe it triggers off of the JTAG signals. Seems unlikely but you never know.
The Quartus project must be setup properly since it thinks it programs successfully.
