Occasional ContributorTechnology Map Viewer Post-Fitting signal names
Hello,
I am using the SignalTap II logic analyzer on Quartus Prime Version : 18.1.1 Build 646 04/11/2019 SJ Standard Edition. I am tracing logic in the Cyclone V SOC to debug a memory-mapped slave interface using the post-fit map viewer. I want to know what the tilde (~) signifies in a signal name. As an example, I have a problem with the decoding of the addresses instantiated in the slave interface. I want to trigger on either slave_reg_read or slave_reg_write. The map shows two signals that I interpret are for slave_reg_read: m0_read and m0_read~0. The LA trace shows that m0_read is active low and m0_read~0. The two signals are in sync. So does the tilde indicate not m0_read?
For slave_reg_write the map shows two signals: m0_write~[0..1]. The LA trace shows that m0_write~1 is active low and m0_write~0 is active high, with both signals in sync. Does the tilde before the [0..1] indicate something?
Thank you in advance.
Names can get distorted through the place and route process. The ~ does not necessarily mean anything other than the name of a signal changed or a new internal signal was created through this process. If you know the signals you want to tap from your design itself, use the Signal Tap pre-synthesis Node Finder filter instead of post-fit nodes you find in the Tech Map Viewer.
