Stratix 10 SX FPGA Level 4 Slave Peripheral Bus Control Configuration

Hello All,

Thanks for reading my problem!

I am working on controlling UART1 in Intel Stratix 10 SX SoC Development Kit output something. I use SignalTap II to simulate and the result is that the output data is in loop of UART1 block register(0xFFC02114), which means UART1 does not do anything after data is received by the UART1 control register.

I meet the same situation on Cyclone V SoC Development Kit. The way I solve this problem is to configure the register named "l4_sp(0xFF800000)". If I set bit 4 in this register, the Lightweight HPS to FPGA AXI bridge is enabled in the main user space so I can access the FPGA memory space through the bus. I am trying to use the same way on Intel Stratix 10 SX SoC Development Kit, but the difference between these two development kits is that Intel Stratix 10 SX SoC Development Kit has secure firewalls. I find I need to configure the bit 0, 8, 16, 24 of L4_PER Security Control Registers (SCR)-noc_fw_l4_per_l4_per_scr(0xFFD21070) to allow the secure and non-secure transactions for UART1, but this register must be configured within "SECURE | PRIVILEGEMODE" access mode.

Could anyone please show me how I can configure this register, or some other ways I can achieve the same goal?

Thanks very much.

PS: I try to configure this register in "u-boot.scr" file like what I see in RocketBoards(https://rocketboards.org/foswiki/Documentation/S10SoCBridgeConfiguration), but I does not work.