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Hans_1st's avatar
Hans_1st
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4 years ago

Stratix 10 SX FPGA Level 4 Slave Peripheral Bus Control Configuration

Hello All, Thanks for reading my problem! I am working on controlling UART1 in Intel Stratix 10 SX SoC Development Kit output something. I use SignalTap II to simulate and the result is that th...
EricMunYew_C_Intel's avatar
EricMunYew_C_Intel
Icon for Frequent Contributor rankFrequent Contributor
4 years ago

I’m glad that your question has been addressed, I now transition this thread to community support. If you have a new question, feel free to open a new thread to get the support from Intel experts. Otherwise, the community users will continue to help you on this thread. Thank you.