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Hans_1st
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4 years ago

Stratix 10 SX FPGA Level 4 Slave Peripheral Bus Control Configuration

Hello All, Thanks for reading my problem! I am working on controlling UART1 in Intel Stratix 10 SX SoC Development Kit output something. I use SignalTap II to simulate and the result is that th...
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Hans_1st
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4 years ago

Thanks for replying！

I checked this web and I had some questions want to ask:

(1) Is this Appendix only based on using ATF (Arm Trusted Firmware) as the Secure Monitor or not? Because EL3 is only generated by building Arm Trusted Firmware.

(2) If I want to use U-Boot as the Secure Monitor (non-ATF way) to control UART1 on L4 Slave Peripheral Bus, I know I can manage/configure secure L3 or L4 registers in "u-boot.scr" file. So how many and what kind of registers should I manage/configure to achieve my goal?