kiransr
Occasional Contributor
Occasional ContributorStratix 10 SOC FPGA LVDS
Hi,
We have LVDS clock & data signal coming from ASIC to stratix 10 SOC FPGA, can we use these signals without any clock recovery logic directly or not
Regards,
Kiran
Forum Discussion
4 Replies
FvMSuper Contributor
Hi,
if you need clock recovery depends on the kind of input signal. A signal comprised of data, bit clock and frame clock, e.g. ADC output doesn't need clock recovery. In any case, there are no LVDS decoding features inside HPS. They have to be implemented in FPGA fabric, data would be transferred to HPS through a bridge.
AqidAyman_AlteraRegular Contributor
Referencing the user guide, the soft clock data recovery (soft-CDR) mode is useful for asynchronous clocking applications.
- AqidAyman_Altera
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- AqidAyman_Altera
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