kiransr
Occasional Contributor
Occasional ContributorStratix 10 SOC FPGA LVDS
Hi, We have LVDS clock & data signal coming from ASIC to stratix 10 SOC FPGA, can we use these signals without any clock recovery logic directly or not Regards, Kiran
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AqidAyman_Altera
Regular Contributor
Regular ContributorI wish to follow up regarding this thread. Are there any more supports needed? If yes, please let me know before I close this thread.
