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kiransr's avatar
kiransr
Icon for Occasional Contributor rankOccasional Contributor
1 year ago

Stratix 10 SOC FPGA LVDS

Hi, We have LVDS clock & data signal coming from ASIC to stratix 10 SOC FPGA, can we use these signals without any clock recovery logic directly or not Regards, Kiran
Fpga Devkit
AqidAyman_Altera's avatar
AqidAyman_Altera
Icon for Regular Contributor rankRegular Contributor
1 year ago

I hope the previous response was sufficient to help you proceed. As we do not receive any response from you on the previous question/reply/answer that we have provided. Please login to ‘https://supporttickets.intel.com/s/?language=en_US’, view details of the desire request, and post a feed/response within the next 15 days to allow me to continue to support you. After 15 days, this thread will be transitioned to community support. The community users will be able to help you on your follow-up questions.