AnuragWho
New Contributor
2 years agoStratix 10 FPGA Recalibration
Hi,
We are trying to implement JESD204B Interface between AFE7900 EVM (Transmitter) and Stratix 10 1SX280LU2F50E1VG EVM (Receiver). To maintain JESD Link Stable, We need to Re-calibrate the FPGA.
The detailed Implementation process of Re-calibration which we tried is attached in the document.
We are not able to complete Re-calibration using the mentioned procedure.
Kindly suggest correct procedure to perform the Re-calibration of the same.