Forum Discussion

AnuragWho's avatar
AnuragWho
Icon for New Contributor rankNew Contributor
2 years ago

Stratix 10 FPGA Recalibration

Hi, We are trying to implement JESD204B Interface between AFE7900 EVM (Transmitter) and Stratix 10 1SX280LU2F50E1VG EVM (Receiver). To maintain JESD Link Stable, We need to Re-calibrate the FPGA. ...
Fpga Devkit
ZH_Intel's avatar
ZH_Intel
Icon for Frequent Contributor rankFrequent Contributor
2 years ago

Hi Anurag,

Apologize for the delayed response as we encounter technical difficulty.

Regarding to your question, you may refer to the JESD204B FPGA IP User guide under chapter 4.4. Clocking Scheme and 4.5. Reset Scheme, this chapter shows how to calibrate the transceiver, and steps to do it.

For more information refer below link:

  1. JESD204B Intel® FPGA IP User Guide - 4.4.5. Transceiver Calibration Clock Source
  2. JESD204B Intel® FPGA IP User Guide - 4.5. Reset Scheme

Hope this answers your question.

Thank you.

Best Regards,

ZH_Intel