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AnuragWho's avatar
AnuragWho
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2 years ago

Stratix 10 FPGA Recalibration

Hi, We are trying to implement JESD204B Interface between AFE7900 EVM (Transmitter) and Stratix 10 1SX280LU2F50E1VG EVM (Receiver). To maintain JESD Link Stable, We need to Re-calibrate the FPGA. ...
Fpga Devkit
ZH_Intel's avatar
ZH_Intel
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2 years ago

Hi Anurag,


Good day.

We do not receive any response from you to the previous reply that I have provided. This thread will be transitioned to community support. If you have a new question, feel free to open a new thread to get the support from Intel experts. Otherwise, the community users will continue to help you on this thread.


Thank you.

Best Regards,

ZH_Intel