Forum Discussion

AnuragWho's avatar
AnuragWho
Icon for New Contributor rankNew Contributor
2 years ago

Stratix 10 FPGA Recalibration

Hi, We are trying to implement JESD204B Interface between AFE7900 EVM (Transmitter) and Stratix 10 1SX280LU2F50E1VG EVM (Receiver). To maintain JESD Link Stable, We need to Re-calibrate the FPGA. ...
Fpga Devkit
ZH_Intel's avatar
ZH_Intel
Icon for Frequent Contributor rankFrequent Contributor
2 years ago

Hi Anurag,

Thank you for reaching out.

Just to let you know that Intel has received your support request and currently we are confirming the details with our internal team.

I shall come back to you with findings.

Thank you for your patience.

Best Regards,

ZH_Intel


  • AnuragWho's avatar
    AnuragWho
    Icon for New Contributor rankNew Contributor
    2 years ago

    Hi,

    Can we have any update on the above query.

    Regards

    Anurag