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Junyong's avatar
Junyong
Icon for Occasional Contributor rankOccasional Contributor
2 years ago
Solved

Rules for pin planner

Hi all,

I'm tyring to compile my project, but I have an error message: can't place node "emif_0_mem_dq(56)~pad" -- illegal location assignment PIN_A37".

I have similar error messages for other pins.

What's the rule for a pin planner?

For your information, I downloaded "Stratix10_PCIeGen3x8_DMA_18_0"

And, I'm trying the project above with my Stratix 10 TX Signal Integrity Dev Kit.

I just changed the device name in the project, and I did auto-upgrade and ran a compilation.

Fpga Devkit
  • AdzimZM_Altera's avatar
    AdzimZM_Altera
    2 years ago

    Hi Junyong,


    The design example that you have downloaded is targeting Stratix 10 GX Development Kit.

    It's cannot be used for Stratix 10 TX Signal Integrity Dev Kit.

    The reason is that the design example is not compatible.


    The error message that you have shown is related to external memory interface.

    The Stratix 10 TX Signal Integrity Dev Kit doesn't has an external memory on the board.


    The pin allocated in the design example is targeting Stratix 10 GX device.

    When changing the to other device, the pin assignment need to change to targeted device pin location.


    There are a lot of differences between the Stratix 10 GX and Stratix 10 TX devkit.

    So you cannot simply run the Stratix 10 GX design example in the Stratix 10 TX devkit.


    You may tried to use the design examples that have been included in the ZIP file of the development kit.


    Regards,

    Adzim


10 Replies

  • FvM's avatar
    FvM
    Icon for Super Contributor rankSuper Contributor
    2 years ago
    Hi,
    presume the device used in the original example design is no Stratix TX and has different pin assignments. emif uses dedicated pins, I would try to use pin assignments from design examples fitting your board.
    I also wonder how you want to implement PCIe example on signal integrity dev kit that has no PCIe interface? I can't imagine that many pin assignments of the PCIe design fits your board.
    • Junyong's avatar
      Junyong
      Icon for Occasional Contributor rankOccasional Contributor
      2 years ago

      Hi FvM,

      Thank you for reply. According to website Intel® Stratix® 10 TX Signal Integrity Dev Kits, "Verify physical medium attachment (PMA) compliance with PCI Express (PCIe), 10G/25G/50G/200G/400G Ethernet, and other major standards" says that Stratix10 Dev Kit supports the PCIe communication protocol.

      Thus, I tried to download the PCIe example and run it to operate the PCIe data transfer. What I need to do is to transmit PICe data by the FPGA.

      Does not Stratix10 Signal Integrity Dev Kit support the PCIe interface?

      Best,

  • Junyong's avatar
    Junyong
    Icon for Occasional Contributor rankOccasional Contributor
    2 years ago

    Hi FvM,

    Thank you for reply. According to website Intel® Stratix® 10 TX Signal Integrity Dev Kits, "Verify physical medium attachment (PMA) compliance with PCI Express (PCIe), 10G/25G/50G/200G/400G Ethernet, and other major standards" says that Stratix10 Dev Kit supports the PCIe communication protocol.

    Thus, I tried to download the PCIe example and run it to operate the PCIe data transfer. What I need to do is to transmit PICe data by the FPGA.

    Does not Stratix10 Signal Integrity Dev Kit support the PCIe interface?

    Best,

  • AdzimZM_Altera's avatar
    AdzimZM_Altera
    Icon for Regular Contributor rankRegular Contributor
    2 years ago

    Hi Junyong,


    The design example that you have downloaded is targeting Stratix 10 GX Development Kit.

    It's cannot be used for Stratix 10 TX Signal Integrity Dev Kit.

    The reason is that the design example is not compatible.


    The error message that you have shown is related to external memory interface.

    The Stratix 10 TX Signal Integrity Dev Kit doesn't has an external memory on the board.


    The pin allocated in the design example is targeting Stratix 10 GX device.

    When changing the to other device, the pin assignment need to change to targeted device pin location.


    There are a lot of differences between the Stratix 10 GX and Stratix 10 TX devkit.

    So you cannot simply run the Stratix 10 GX design example in the Stratix 10 TX devkit.


    You may tried to use the design examples that have been included in the ZIP file of the development kit.


    Regards,

    Adzim


    • Junyong's avatar
      Junyong
      Icon for Occasional Contributor rankOccasional Contributor
      2 years ago

      Hi Adzim,

      Thanks for your reply. It was very helpful to me.

      The conclusion is that I can't use the Stratix10 Tx Signal Integrity Dev Kit to run the project of PCIe.

      Then, I have a question regarding the Stratix10 Tx SI Dev Kit. Doesn't this kit support the PCIe data transmission, becuase it has no PCIe connector?

      Best,

      Junyong

      • FvM's avatar
        FvM
        Icon for Super Contributor rankSuper Contributor
        2 years ago

        Hi,
        the conclusion is that you can't use the Stratix 10 GX design example because it doesn't fit your board. You can generate a PCIe example design with a pin assignment fitting the board, but it won't directly plug into a standard PCIe PC Slot, e.g. use some kind of adapter.

    • Junyong's avatar
      Junyong
      Icon for Occasional Contributor rankOccasional Contributor
      2 years ago

      Thank you for reply, AdzimZM.

      Your reply is really helpful to me.

      Best,

      Junyong

  • AdzimZM_Altera's avatar
    AdzimZM_Altera
    Icon for Regular Contributor rankRegular Contributor
    2 years ago

    I’m glad that your question has been addressed, I now transition this thread to community support. If you have a new question, feel free to open a new thread to get the support from Intel experts. Otherwise, the community users will continue to help you on this thread. Thank you.