Forum Discussion
Occasional ContributorRules for pin planner
Hi Junyong,
The design example that you have downloaded is targeting Stratix 10 GX Development Kit.
It's cannot be used for Stratix 10 TX Signal Integrity Dev Kit.
The reason is that the design example is not compatible.
The error message that you have shown is related to external memory interface.
The Stratix 10 TX Signal Integrity Dev Kit doesn't has an external memory on the board.
The pin allocated in the design example is targeting Stratix 10 GX device.
When changing the to other device, the pin assignment need to change to targeted device pin location.
There are a lot of differences between the Stratix 10 GX and Stratix 10 TX devkit.
So you cannot simply run the Stratix 10 GX design example in the Stratix 10 TX devkit.
You may tried to use the design examples that have been included in the ZIP file of the development kit.
Regards,
Adzim
Occasional ContributorHi FvM,
Thank you for reply. According to website Intel® Stratix® 10 TX Signal Integrity Dev Kits, "Verify physical medium attachment (PMA) compliance with PCI Express (PCIe), 10G/25G/50G/200G/400G Ethernet, and other major standards" says that Stratix10 Dev Kit supports the PCIe communication protocol.
Thus, I tried to download the PCIe example and run it to operate the PCIe data transfer. What I need to do is to transmit PICe data by the FPGA.
Does not Stratix10 Signal Integrity Dev Kit support the PCIe interface?
Best,
