Hi,When I used Quartus to compile for a cyclone V device I got an warning, which was just the one in the link below. I followed the Workaround/Fix part of the link to try to remove the warning but failed:https://www.intel.com/content/www/us/en/programmable/support/support-resources/knowledge-base/solutions/rd09192012_189.htmlThere are some information about the PLL for the project:There is only one PLL instance in the project, the type is integer PLL and normal mode with automatic reset;When I generated PLL I didn't see the options for compensation;When I set the "Match PLL Compensation Clock" assignment, I chose the node that could have a green tick ahead the assignment, which was end with altera_pll:altera_pll_i|general[0].gpll.My questions are:Whether the PLL clocks are not compensated if the warning is there?What can I do to eliminate the warning?Thank you.Best regards,Ross

Hi RLee42!First of all, there are different compensation modes in Altera PLL IP core, so it's strange that you didn't see them. You can read about them here : https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/ug/altera_pll.pdf - Operation modes.You can choose them from the GUI - you already made a selection (normal).About your questions - In that case fitter will compensate all PLL clocks like this : " Normal mode—the PLL feedback path source is a global or regional clock network, minimizing clock delay from the input clock pin to the core registers through global or regional clock network."The workaround should help - I successfully eliminated problem in my own project.Hope that helps.--Best Regards,Ivan

Yes, you should be able to see each of compensation in PLL IP GUI. Just select any of them and see if it will get rid of the warning.

Please use this command in qsf to set which clock output to be compensated => set_instance_assignment -name MATCH_PLL_COMPENSATION_CLOCK ON -to "<PLL name>|outclk_wire[0]"

Hi lvan,Thank you for your time.I did choose "normal" when I generated PLL and I thought Quartus should know the way to compensate, however, I still got a warning as below:Warning (177007): PLL(s) placed in location FRACTIONALPLL_X0_Y1_N0 do not have a PLL clock to compensate specified - the Fitter will attempt to compensate all PLL clocks.Then I assumed that there might be some extra options for compensation which I missed. That's why I said "When I generated PLL I didn't see the options for compensation".Thank you.Best Regards,Ross

Hi RLee42!Ok, I see.I can say that in most cases you can ignore that warning, but to eliminate it, try what GNg suggests below -> => set_instance_assignment -name MATCH_PLL_COMPENSATION_CLOCK ON -to "<PLL name>|outclk_wire[0]"--Best Regards,Ivan

"Match PLL Compensation Clock" assignment doesn't work

11 Replies

IDeyn
Contributor
7 years ago
Hi RLee42!
First of all, there are different compensation modes in Altera PLL IP core, so it's strange that you didn't see them. You can read about them here : https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/ug/altera_pll.pdf - Operation modes.
You can choose them from the GUI - you already made a selection (normal).
About your questions -
In that case fitter will compensate all PLL clocks like this : " Normal mode—the PLL feedback path source is a global or regional clock network, minimizing clock delay from the input clock pin to the core registers through global or regional clock network."
The workaround should help - I successfully eliminated problem in my own project.
Hope that helps.
--
Best Regards,
Ivan
- RLee42
  Occasional Contributor
  7 years ago
  Hi lvan,
  
  Thank you for your time.
  
  I did choose "normal" when I generated PLL and I thought Quartus should know the way to compensate, however, I still got a warning as below:
  
  Warning (177007): PLL(s) placed in location FRACTIONALPLL_X0_Y1_N0 do not have a PLL clock to compensate specified - the Fitter will attempt to compensate all PLL clocks.
  
  Then I assumed that there might be some extra options for compensation which I missed. That's why I said "When I generated PLL I didn't see the options for compensation".
  
  Thank you.
  Best Regards,
  Ross
  - IDeyn
    Contributor
    7 years ago
    Hi RLee42!
    Ok, I see.
    I can say that in most cases you can ignore that warning, but to eliminate it, try what GNg suggests below -> => set_instance_assignment -name MATCH_PLL_COMPENSATION_CLOCK ON -to "<PLL name>|outclk_wire[0]"
    --
    Best Regards,
    Ivan
GuaBin_N_Intel
Contributor
7 years ago
Yes, you should be able to see each of compensation in PLL IP GUI. Just select any of them and see if it will get rid of the warning.
GuaBin_N_Intel
Contributor
7 years ago
Please use this command in qsf to set which clock output to be compensated => set_instance_assignment -name MATCH_PLL_COMPENSATION_CLOCK ON -to "<PLL name>|outclk_wire[0]"
- RLee42
  Occasional Contributor
  7 years ago
  Hi GNg,
  
  Thank you for your reply.
  
  As Even I chose "Normal mode" when generated the PLL, I still got a warning as below:
  
  Warning (177007): PLL(s) placed in location FRACTIONALPLL_X0_Y1_N0 do not have a PLL clock to compensate specified - the Fitter will attempt to compensate all PLL clocks
  
  Then I also tried adding a command in qsf by using assignment editor.
  I tried two commands separately which could have a green tick in assignment editor as below (my PLL didn't have outclk_wire[0], which was generated by Quartus Lite 18.1 for cyclone V):
  
  set_instance_assignment -name MATCH_PLL_COMPENSATION_CLOCK ON -to "pll:u_pll|pll_0002:pll_inst|altera_pll:altera_pll_i|general[0].gpll"
  set_instance_assignment -name MATCH_PLL_COMPENSATION_CLOCK ON -to "pll:u_pll|pll_0002:pll_inst|altera_pll:altera_pll_i|general[0].gpll~FRACTIONAL_PLL"
  
  The first one was generated by choosing a node in assignment editor.
  The second one was copied and pasted into the assignment editor from the info that in Warning (177007).
  
  However, I got another warning for this command:
  
  Warning (171167): Found invalid Fitter assignments. See the Ignored Assignments panel in the Fitter Compilation Report for more information.
  
  So, this command didn't work, though I thought the clock output was correct.
  
  Thank you.
  
  Best regards,
  Ross
GuaBin_N_Intel
Contributor
7 years ago
I extracted the command from my PLL design built in Quartus version 18.1. You should see the clock name "~outclk_wire[0]". set_instance_assignment -name MATCH_PLL_COMPENSATION_CLOCK ON -to "pll_150out:pll_150out_inst|pll_150out_0002:pll_150out_inst|altera_pll:altera_pll_i|outclk_wire[0]" Another way to find its clock output name is from Fitter report. Go to Fitter>Resource section>Global & other fast signals> find that corresponding PLL's signal suffix with "outclk_wire"
- RLee42
  Occasional Contributor
  7 years ago
  Hi GNg,
  Thank you and I found it at last.
  Best regards,
  Ross

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"Match PLL Compensation Clock" assignment doesn't work

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