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RLee42
Occasional Contributor
Occasional Contributor"Match PLL Compensation Clock" assignment doesn't work
Hi, When I used Quartus to compile for a cyclone V device I got an warning, which was just the one in the link below. I followed the Workaround/Fix part of the link to try to remove the warning b...
GuaBin_N_Intel
Contributor
ContributorI extracted the command from my PLL design built in Quartus version 18.1. You should see the clock name "~outclk_wire[0]".
set_instance_assignment -name MATCH_PLL_COMPENSATION_CLOCK ON -to "pll_150out:pll_150out_inst|pll_150out_0002:pll_150out_inst|altera_pll:altera_pll_i|outclk_wire[0]"
Another way to find its clock output name is from Fitter report. Go to Fitter>Resource section>Global & other fast signals> find that corresponding PLL's signal suffix with "outclk_wire"
RLee42Occasional Contributor
Occasional ContributorHi GNg,
Thank you and I found it at last.
Best regards,
Ross
