Forum Discussion
- RLee427 years ago
Occasional Contributor
Hi GNg,
Thank you for your reply.
As Even I chose "Normal mode" when generated the PLL, I still got a warning as below:
Warning (177007): PLL(s) placed in location FRACTIONALPLL_X0_Y1_N0 do not have a PLL clock to compensate specified - the Fitter will attempt to compensate all PLL clocks
Then I also tried adding a command in qsf by using assignment editor.
I tried two commands separately which could have a green tick in assignment editor as below (my PLL didn't have outclk_wire[0], which was generated by Quartus Lite 18.1 for cyclone V):
set_instance_assignment -name MATCH_PLL_COMPENSATION_CLOCK ON -to "pll:u_pll|pll_0002:pll_inst|altera_pll:altera_pll_i|general[0].gpll"
set_instance_assignment -name MATCH_PLL_COMPENSATION_CLOCK ON -to "pll:u_pll|pll_0002:pll_inst|altera_pll:altera_pll_i|general[0].gpll~FRACTIONAL_PLL"
The first one was generated by choosing a node in assignment editor.
The second one was copied and pasted into the assignment editor from the info that in Warning (177007).
However, I got another warning for this command:
Warning (171167): Found invalid Fitter assignments. See the Ignored Assignments panel in the Fitter Compilation Report for more information.
So, this command didn't work, though I thought the clock output was correct.
Thank you.
Best regards,
Ross