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Fred_Barkins's avatar
Fred_Barkins
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1 month ago

Mandelbrot viewer on Cyclone V - Platform Designer layout

Hello,

I’ve been trying to implement on my DE1-SoC an outstanding Mandelbrot Viewer written by 3 fellows at Cornell, which published partial information in an online available final report 

I manage to compile the C++ code and perform a sanity check on my x86 host:​

And I manage to compile the C++ to run on the DE1-SoC HPS:

Also, I got Quartus to compile the Verilog provided in the report, though it’s not in its final, working form.

I’m pretty sure my problem is in the Platform Designer (formerly Qsys) layout. Been trying many variations around this layout for several weeks, but with no success:​

I chose the components to my best understanding based the report, that mentions:

"The communication between the FPGA and the hard processor system happens over a memory-mapped AXI bus. Requests for tiles are placed into a FIFO on the FPGA, and solved tile data is written out into external SDRAM memory.

Requests from the HPS are sent over the AXI bus into a FIFO located on the FPGA. A request distributor then pulls the message off of the FIFO using the avalon streaming interface and handles it. (I assume this is with reference to request_distributor.sv attached in report)

As the solvers solve pixels of the output tile, they write the results to SDRAM. Arbitration logic collects results from any solvers which are ready to write. (I assume this is with reference to write_arbitrator.sv attached in report)"

Additional info: To my understanding, a top module (not attached to the report) is probably instantiating a multi_tile_solver.sv module and a module from Platform Designer, nothing more. As can be seen in the files in the report, multi_tile_solver.sv instantiates a request_distributor.sv module, a write_arbitrator.sv module, and NUM_SOLVERS tile_solver_legit.sv modules. Each tile_solver_legit.sv instantiates a solver.v, which instantiates a solver_control.v and a solver_datapath.v. It uses on-chip SRAM in the form of M10K block, which are created from the verilog source code, rather than having anything to do with the Platform Designer layout.

I think I’m pretty close to running this amazing project, yet have been stuck on this platform designer layout and don’t succeed in finalizing. Any help would be much appreciated.

Fpga Devkit
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6 Replies

  • KianHinT_altera's avatar
    KianHinT_altera
    Icon for Frequent Contributor rankFrequent Contributor
    1 month ago

    Thanks EV for the support.

    Hi Fred,

    Just wondering about the status for this case? Do you require further help , otherwise I would like to set this case to closure and transition to community support.

    Thanks

    Regards

    Kian

  • EstebanVV_Altera's avatar
    EstebanVV_Altera
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    1 month ago

    You can do this...

    NOTE 1: when you set 0x0, then you access this device from the HPS using the address 0xC000_0000 (you are accounting for the offset of the FULL bridge, plus the base address of your device). This is the access point to your "data"

    NOTE 2: "in-crs" can also be connected to the Full Bridge, this is the access for the "control registers" of the "FIFO IP" see: 

    https://docs.altera.com/r/docs/683130/25.3/embedded-peripherals-ip-user-guide/functional-description?tocId=z_fqMkXoilssdb5huYtRzg

    When you connect this, it will require an address. Again, when using the HPS to access the cotrol registers you need the address = 0xc000_0000 (full bridge) + <BASE defined by you>

    NOTE3: The "out" is already a "avalon streaming interface". I asumme you IP already has a "Avalon streaming receiver". Maybe this receiver is the "sink" you are poiting out, but I dont know this IP (It is not supported by us)

    I cannot comment in further connections to custom IP, I can only help you with generic Platform Designer and Quartus questions. If you use Altera IP, most documentation is available and you can find the list of control registers to configure them.

    Good luck with your project.

    ~E.V.

    • Fred_Barkins's avatar
      Fred_Barkins
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      1 month ago

      Thank you very much for your replies and assistance. I think I might be getting closer.

      A big part of what I'm trying to find out but didn't manage to, is whether or not a custom component is even needed. I'm writing again all of the communication that has to be done:

      HPS --> FPGA: FIFO, and then messages "pulling" off of the FIFO using the avalon streaming interface

      FPGA --> HPS: SDRAM (which is external to the FPGA).

      1. In the most general case, to implement this kind of communication, does this necessarily require a custom module that has the verilog source file/files included in it?

      from what I understand from the workflow, there are two methods when working with Platform Designer: the first one, which is the one I thought was more common, is to make the layout wiring and address mapping in the gui, export conduits, and then use the auto generated code to tie these conduits to logic in the verilog source code.

      the second one, which i'm less familiar with and trying to understand if necessary in this case, is creating a new custom component add adding files to it, use the "analyze synthsis files" and make the gui wiring.

      2. Addition information: it's mentioned that: "The FIFO instantiated on the FPGA, along with the Avalon bus structure and SDRAM controller that we used, were all Altera". I take this as supporting the first kind of workflow - without a custom component. Does this make sense? if so, please help me figure out the layout, because I've really been trying all my best and couldn't figure it out for several weeks. 

      In order to add a SDRAM controller, i went to an older quartus version (20.1 because the SDRAM Controller Intel FPGA IP seems to no longer be supported with 24.1 and doesn't appear in the catalog):

      Please note that:

       the "out" interface of the fifo couldn't be wired to anything in the screenshot above if there was no sink in the entire design to accept it. So what I did, is add a new custom component but only because i didn't know what altera IP i should use. As I explained above, when searching in the catalog, i didn't find the right thing, maybe i'm wrong? attaching again:

      all the options below, which were cut out from the screenshot, are non standard too.

       This "custom component" of mine has nothing to do with my verilog source code, no files added in it. It only includes simple three interfaces: clock, reset and avalon_streaming_sink:

      in order to accept the fifo_0.out source.

      3. Do you think that the platform designer layout shown above should be sufficient to implement the communication of the problem described in the beginning of this message? what do i need to know about setting the base address and span of the SDRAM Controller component as a slave on the h2f axi master?

       

      Thank you very much

      • EstebanVV_Altera's avatar
        EstebanVV_Altera
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        1 month ago

        Hi,

        Answering your questions.

        -- Regarding 1: Yes, at you said there are two options for you to included a custom IP into your design (a collection of Verilog files)

        a. "Wrapping" the IP in a structure that can be instantiated by Platform Designer, following 

        https://docs.altera.com/r/docs/683609/25.1.1/quartus-prime-pro-edition-user-guide-platform-designer/creating-platform-designer-components and How To Create A Custom Platform Designer Component That Uses Intel IP Components | Altera Community

        b. As you said, you can export the interfaces from PD of other IP and make it visible to the <top_level> HDL file. Then use pure HDL language to connect your system.

        -- Regarding 2: The SDRAM controller is not longer supported by standard. Please see: https://community.altera.com/discussions/boards-and-dev-kits/de10-lite-and-sdram-controller-ip/348588

        (It is always a good idea to search in the forum for issues, as they might be already documented)

        " the "out" interface of the fifo couldn't be wired to anything in the screenshot above if there was no sink in the entire design to accept it." : well, I don't know your IP... but from what you have been telling me, your IP should have a streaming interface that "accepts" the streaming interface output from the FIFO

        I think what you are missing is this "A request distributor then pulls the message off of the FIFO using the avalon streaming interface, and either sends it, one word at a time, to an unoccupied tile solver or waits if they are all occupied."

        Again, I don't know your design, BUT "request distributor" is the key word. Is this something you have to implement?  is this included in your source files? This is not certainly an IP provided by Altera.

        --- Regarding 3. Your layout seems ok. But keep in mind your software, as It might have the addresses already in place and expected for each device.

        ~E.V.

  • EstebanVV_Altera's avatar
    EstebanVV_Altera
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    1 month ago

    Hello Fred_Barkins​, this is seems to be an specific project not supported directly by Altera, hence the best suggestion could be to make contact with the creator for especifics.

    However, we can help you understanding the communication between the HPS (Hard Processor System) and the communication with an FPGA soft device. It seems to me that your program wants to write "tiles into a FIFO". For this you have to connect the "Avalon Memory Map Slave" of the FIFO IP to any of the H2F axi masters. The using memory map addressing, making sure you have the correct address. 

    Pleasee see: 

    https://www.intel.com/content/www/us/en/programmable/hps/cyclone-v/hps.html and 

    https://www.intel.com/content/www/us/en/programmable/hps/cyclone-v/hps.html

    and note the values "hps2fpgaslaves" and "lwfpgaslaves"

    If you use "FPGA Slaves Accessed Via HPS2FPGA AXI Bridge" then your device address would be 0xC0000000 + <device_address>.

    Then you can retrieve values from the SD RAM using the same mechanism

     

    • Fred_Barkins's avatar
      Fred_Barkins
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      1 month ago

      Thank you very much for your response. 

      I’m trying to implement what you’re saying as components and wiring.

      1. You mentioned:

      connect the "Avalon Memory Map Slave" of the FIFO IP to any of the H2F axi masters.

      I’ll be using the full AXI bus (not the lightweight), so does your sentence mean that I should wire the Avalon FIFO Memory Intel FPGA IP → “in” interface, of type Avalon MM Slave to the h2f_axi_master interface of the hps0 component like shown below? What about in_csr and other interfaces of the FIFO?

      If the answer is yes, is this the interface I should match 0xC000_0000 to? The HPS side code does refer to this address. I guess not fifo_0.in, be cause i get the error:
      Error: prelim_qsys.hps_0.h2f_axi_master: fifo_0.in (0xc0000000..0xc0000007) is outside the master's address range (0x0..0x3fffffff).

      2. Still regarding the HPS → FPGA path through the FIFO, it’s stated that the verilog does the following: "A module named “request distributor” pulls the message off of the FIFO using the Avalon streaming interface and handles it." Can you please relate to how the Avalon streaming interface should be used here? Which IP should I add on Platform Designer? I’ll mention that this “request distributor” module has input signals: “in_data”, “in_valid”, “in_end_of_stream”, which suggest a streaming interface rather than a memory mapped interface. When I searched in the catalog, these are the results that came up, and I don’t know which one I should be using, if at all:

      The only other thing I could think of is adding a custom component and under “Signals and Interfaces” add “Avalon Streaming Source” and “Avalon Streaming Sink” interfaces manually, but that doesn’t seem right. And even if I did, I don’t know how its interfaces should be wired:

      The GUI will only let me alternate the "avalon_streaming_sink" interface of type "Avalon Streaming Sink" between the same component's "avalon_streaming_source" interface of type "Avalon Streaming Source":

      or the "out" interface of type "Avalon Streaming Source" in the fifo_0 component:

      but not both at the same time.

      3. Regarding FPGA→HPS, you mentioned:

      Then you can retrieve values from the SD RAM using the same mechanism

      Can you please help me understand how to turn this to Platform Designer components and wiring? I’ll mention that the verilog module that’s in charge for the “writing arbitration” has output lines (of SystemVerilog’s type logic): “out_data”, “out_address”, “out_write_en”. I’m assuming that there should be some component that should be connected in the gui to the f2h_axi_slave interface of the hps component?

      Thank you very much for your  help