Occasional ContributorIssues when testing DMA feature provided by Avalon MM+ IP with S10 GX dev kit card on Ubuntu 18.04
I have installed s10 GX dev kit fpga card on Ubuntu 18.04 and program the Avalon MM+ Hard IP to the card.
While I meet some issues when testing the DMA feature.
For the test application which locates at ~/avmm_bridge_512_0_example_design/software/user/example/intel_fpga_pcie_link_test, all the test mode cannot run successfully.
For example, the first test, Doing 100 writes and 100 reads, failed. I put the results of first 10 tries below.
At dword 0x0 Wrote 0x120aed54 Read 0xffffffff At dword 0x1 Wrote 0x4db4d210 Read 0xffffffff At dword 0x2 Wrote 0x616cd2bb Read 0xffffffff At dword 0x3 Wrote 0x29ad0aff Read 0xffffffff At dword 0x4 Wrote 0x31f54bf7 Read 0xffffffff At dword 0x5 Wrote 0x7f08785d Read 0xffffffff At dword 0x6 Wrote 0x4fde1236 Read 0xffffffff At dword 0x7 Wrote 0x401d6525 Read 0xffffffff At dword 0x8 Wrote 0x44a0f03b Read 0xffffffff At dword 0x9 Wrote 0x49ebcbdc Read 0xffffffff
For each time testing, the result of reading from the memory is 0xffffffff. While it shows reading and writing operaions don't meet errors. Only the numbers don't match.
Number of write errors: 0 Number of read errors: 0 Number of dword mismatches: 100
While I look into the code, I do not find where the device memory address is initialized for device memory. It is just initialized to NULL.
char *addr = NULL;
I am wondering why the test application does not use memory map to get a address mapping to the FPGA card memory. I'm not sure if it is initialized in other functions and whether the address(NULL) is the reason to cause the mismatches.
However, other testing mode cannot work as well. So maybe there are caused by other reasons.
When I installed the PCIe driver for the FPGA card, as the provided driver code is for CentOS, I modified some code to make it could be successfully installed on Ubuntu. Not sure if my modifications will cause any issue.
Hope someone have ideas on the issues I've met. Thank you and look forward to reply.
The problem you seen might related to below KBD
Why does the Intel® Stratix® 10 Avalon®-MM Interface for PCIe* with DMA example design fail the link test and the DMA test when using the default selected BAR0?DescriptionWhen the internal DMA Descriptor Controller is enabled, the BAR0 Avalon®-MM master is not available for general-purpose usage. The DMA Descriptor Controller uses this BAR0 interface through which the host CPU programs in the descriptor table.
The intel_fpga_pcie_link_test user application selects BAR0 as default when it's initially executed. If the user forgets to change to BAR2, which is where the onchip memory is attached, then both the link test and the DMA test will fail.
ResolutionThe user must change to BAR2 before executing the link test and the DMA test.
See the execution transcript of the intel_fpga_pcie_link_test user application below for how to change to BAR2.
~$ sudo ./intel_fpga_pcie_link_test
*********************************************************
Intel FPGA PCIe Link Test
Version 2.0
0: Automatically select a device
1: Manually select a device
*********************************************************
> 0
Opened a handle to BAR 0 of a device with BDF 0x1300
*********************************************************
0: Link test - 100 writes and reads
1: Write memory space
2: Read memory space
3: Write configuration space
4: Read configuration space
5: Change BAR
6: Change device
7: Enable SRIOV
8: Do a link test for every enabled virtual function
belonging to the current device
9: Perform DMA
10: Quit program
*********************************************************
> 5
Changing BAR...
Enter BAR number (-1 for none):
> 2
Successfully changed BAR!
