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He4Forum's avatar
He4Forum
Icon for Occasional Contributor rankOccasional Contributor
3 years ago
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Issues when testing DMA feature provided by Avalon MM+ IP with S10 GX dev kit card on Ubuntu 18.04

I have installed s10 GX dev kit fpga card on Ubuntu 18.04 and program the Avalon MM+ Hard IP to the card. While I meet some issues when testing the DMA feature. For the test application which lo...
  • skbeh's avatar
    skbeh
    3 years ago

    The problem you seen might related to below KBD

    https://www.intel.com/content/www/us/en/programmable/support/support-resources/knowledge-base/ip/2019/why-does-the-intel--stratix--10-avalon--mm-interface-for-pci-exp.html


    Why does the Intel® Stratix® 10 Avalon®-MM Interface for PCIe* with DMA example design fail the link test and the DMA test when using the default selected BAR0?

    Description

    When the internal DMA Descriptor Controller is enabled, the BAR0 Avalon®-MM master is not available for general-purpose usage. The DMA Descriptor Controller uses this BAR0 interface through which the host CPU programs in the descriptor table.

    The intel_fpga_pcie_link_test user application selects BAR0 as default when it's initially executed. If the user forgets to change to BAR2, which is where the onchip memory is attached, then both the link test and the DMA test will fail.

    Resolution

    The user must change to BAR2 before executing the link test and the DMA test.

    See the execution transcript of the intel_fpga_pcie_link_test user application below for how to change to BAR2.

    ~$ sudo ./intel_fpga_pcie_link_test

    *********************************************************

    Intel FPGA PCIe Link Test

    Version 2.0

    0: Automatically select a device

    1: Manually select a device

    *********************************************************

    > 0

    Opened a handle to BAR 0 of a device with BDF 0x1300

    *********************************************************

    0: Link test - 100 writes and reads

    1: Write memory space

    2: Read memory space

    3: Write configuration space

    4: Read configuration space

    5: Change BAR

    6: Change device

    7: Enable SRIOV

    8: Do a link test for every enabled virtual function

    belonging to the current device

    9: Perform DMA

    10: Quit program

    *********************************************************

    > 5

    Changing BAR...

    Enter BAR number (-1 for none):

    > 2

    Successfully changed BAR!