Ignored Buffers in Delay Line Design

Hi everyone,

I am currently designing a delay chain using Cyclone V and come across a strange problem.

The design in verilog is shown below:

module delay_chain(delay_in,delay_out);

input wire delay_in;

output wire delay_out;

wire buff1,buff2,buff3;

bufif0 d1(buff1,delay_in,1'b0);

bufif0 d2(buff2,buff1,1'b0);

bufif0 d3(buff3,buff2,1'b0);

bufif0 d4(delay_out,buff3,1'b0);

endmodule

To prevent compiler from ignoring them during synthesis, my setting is shown in the attachment file.

Though I turned off all buffers', including soft ones, optimization choices, the post-mapping and post-fitting viewer still do not show my design. More confusing thing is the RTL Viewer indeed shows that my design module exists.

During the placement and fitting stage, Quartus generates warning that my module does not exist, which means it is some how ignored by the compiler. (Warning (15706): Node "delay_detection:UUT|delay_chain:delay_DUT" is assigned to location or region, but does not exist in design)

Does anyone know why this the case? If this issue cannot be solved by the compiler's settings, could anyone recommend a way of cascading four logic units? (I have tried AND, Or and ordinary buffers, but all failed. I do not want to use adder chain, as I want to know the minimum resolution of a logic gate in the cyclone V.)

Thank you very much!

Mingqiang