Ignored Buffers in Delay Line Design

Hi Mingqiang,

Below is the HDL that works

module delay_chain(delay_in,delay_out);

input wire delay_in;

output wire delay_out /* synthesis keep*/;

wire buff /* synthesis keep*/;

wire buff2/* synthesis keep*/;

wire buff3/* synthesis keep*/;

assign delay_out = buff3;

assign buff3 = buff2;

assign buff2 = buff;

assign buff = delay_in;

endmodule

Thanks

Best regards,

KhaiY