Forum Discussion
cosx
Occasional Contributor
Occasional ContributorIgnored Buffers in Delay Line Design
Hi everyone, I am currently designing a delay chain using Cyclone V and come across a strange problem. The design in verilog is shown below: module delay_chain(delay_in,delay_out); input wire de...
KhaiChein_Y_Intel
Regular Contributor
Regular ContributorHi Mingqiang,
Below is the HDL that works
module delay_chain(delay_in,delay_out);
input wire delay_in;
output wire delay_out /* synthesis keep*/;
wire buff /* synthesis keep*/;
wire buff2/* synthesis keep*/;
wire buff3/* synthesis keep*/;
assign delay_out = buff3;
assign buff3 = buff2;
assign buff2 = buff;
assign buff = delay_in;
endmodule
Thanks
Best regards,
KhaiY
