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cosx's avatar
cosx
Icon for Occasional Contributor rankOccasional Contributor
5 years ago

Ignored Buffers in Delay Line Design

Hi everyone, I am currently designing a delay chain using Cyclone V and come across a strange problem. The design in verilog is shown below: module delay_chain(delay_in,delay_out); input wire de...
cosx's avatar
cosx
Icon for Occasional Contributor rankOccasional Contributor
5 years ago

Hi KhaiY,

Thank you very much! I have attached the file for your reference.

Thank you!

Mingqiang

    • KhaiChein_Y_Intel's avatar
      KhaiChein_Y_Intel
      Icon for Regular Contributor rankRegular Contributor
      5 years ago

      Hi Mingqiang,

      We do not receive any response from you to the previous question/reply/answer that I have provided. This thread will be transitioned to community support. If you have a new question, feel free to open a new thread to get the support from Intel experts. Otherwise, the community users will continue to help you on this thread. Thank you

      Best regards,

      KhaiY