Forum Discussion

cosx's avatar
cosx
Icon for Occasional Contributor rankOccasional Contributor
5 years ago

Ignored Buffers in Delay Line Design

Hi everyone, I am currently designing a delay chain using Cyclone V and come across a strange problem. The design in verilog is shown below: module delay_chain(delay_in,delay_out); input wire de...
KhaiChein_Y_Intel's avatar
KhaiChein_Y_Intel
Icon for Regular Contributor rankRegular Contributor
5 years ago

Hi Mingqiang,

You have mentioned the software issues Warning (15706): Node "delay_detection:UUT|delay_chain:delay_DUT" is assigned to location or region, but does not exist in design) during the compilation. I would like to check if this is being optimized away during the compilation. Could you share the design.qar and testbench file for investigation? To generate the file, click on Project > Archive Project > Archive.

Thanks.

Best regards,

KhaiY