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cosx's avatar
cosx
Icon for Occasional Contributor rankOccasional Contributor
5 years ago

Ignored Buffers in Delay Line Design

Hi everyone, I am currently designing a delay chain using Cyclone V and come across a strange problem. The design in verilog is shown below: module delay_chain(delay_in,delay_out); input wire de...
KhaiChein_Y_Intel's avatar
KhaiChein_Y_Intel
Icon for Regular Contributor rankRegular Contributor
5 years ago

Hi Mingqiang,

Could you share a simple test case for investigation? What is the software edition and version you are using?

Thanks.

Best regards,

KhaiY

  • cosx's avatar
    cosx
    Icon for Occasional Contributor rankOccasional Contributor
    5 years ago

    Hi KhaiY,

    Thank you so much for your help!

    May I ask the test case here you refer to is simulation or real test on board?

    If it is simulation, I have done RTL simulation using Modelsim, but does not show any effect on delay. (I guess this is due to failure of low level simulation in modelsim)

    The software edition is Quartus Lite 19.1, do you think the Lite Edition is not that smart to map the code into the hardware?

    Thanks!

    Mingqiang