huge delay inserted by Quartus 19.3 pro on the Arria 10 FPGA

Could I use (to prevent quartus doing timing analysis on the combinational loop) MAX_SCC_SIZE?

I've been looking in the synthesis log,

and for both the arria10 and stratix 10 quartus synthesis have the intention to turn the Preset/clear register into a latch:

Warning(13310): Register "rfd_ic_i|u_top|u_core|u_atlas|A_flexcomm_array[1].A_flexcomm|A_flexcomm|A_bi2c_gen.A_bi2c_core|timeout_detect_inst|stop_stage2" is converted into an equivalent circuit using register "rfd_ic_i|u_top|u_core|u_atlas|A_flexcomm_array[1].A_flexcomm|A_flexcomm|A_bi2c_gen.A_bi2c_core|timeout_detect_inst|stop_stage2~synth" and latch "rfd_ic_i|u_top|u_core|u_atlas|A_flexcomm_array[1].A_flexcomm|A_flexcomm|A_bi2c_gen.A_bi2c_core|timeout_detect_inst|stop_stage2~synth"

Warning(13310): Register "rfd_ic_i|u_top|u_core|u_atlas|A_flexcomm_array[1].A_flexcomm|A_flexcomm|A_bi2c_gen.A_bi2c_core|slave_inst|pending_i_capture" is converted into an equivalent circuit using register "rfd_ic_i|u_top|u_core|u_atlas|A_flexcomm_array[1].A_flexcomm|A_flexcomm|A_bi2c_gen.A_bi2c_core|slave_inst|pending_i_capture~synth" and latch "rfd_ic_i|u_top|u_core|u_atlas|A_flexcomm_array[1].A_flexcomm|A_flexcomm|A_bi2c_gen.A_bi2c_core|slave_inst|pending_i_capture~synth"

Warning(13004): Presettable and clearable registers converted to equivalent circuits with latches. Registers power-up to an undefined state, and DEVCLRn places the registers in an undefined state.

Warning(13310): Register "rfd_ic_i|u_top|u_core|u_atlas|A_flexcomm_array[1].A_flexcomm|A_flexcomm|A_bi2c_gen.A_bi2c_core|timeout_detect_inst|stop_stage2" is converted into an equivalent circuit using register "rfd_ic_i|u_top|u_core|u_atlas|A_flexcomm_array[1].A_flexcomm|A_flexcomm|A_bi2c_gen.A_bi2c_core|timeout_detect_inst|stop_stage2~synth" and latch "rfd_ic_i|u_top|u_core|u_atlas|A_flexcomm_array[1].A_flexcomm|A_flexcomm|A_bi2c_gen.A_bi2c_core|timeout_detect_inst|stop_stage2~synth"

Warning(13310): Register "rfd_ic_i|u_top|u_core|u_atlas|A_flexcomm_array[1].A_flexcomm|A_flexcomm|A_bi2c_gen.A_bi2c_core|slave_inst|pending_i_capture" is converted into an equivalent circuit using register "rfd_ic_i|u_top|u_core|u_atlas|A_flexcomm_array[1].A_flexcomm|A_flexcomm|A_bi2c_gen.A_bi2c_core|slave_inst|pending_i_capture~synth" and latch "rfd_ic_i|u_top|u_core|u_atlas|A_flexcomm_array[1].A_flexcomm|A_flexcomm|A_bi2c_gen.A_bi2c_core|slave_inst|pending_i_capture~synth"

So I guess the difference between the Stratix 3 and the Arria 10 is that timing analyzer has changed between quartus 13.1 and quartus 19.3 on latches, is it?

There is no report of combinational loop in the Quartus 13.1 when latches are asserted to solve the clear/preset reg by synplify pro (and of course Quartus does not see preset/clear as it has already been converted by Synplify pro).

I can see this under the timing analyzer/check Timing/latches:

Analyzed unsupported latch type as a combinational loop

I have added the synthesis syn_keep =1 attributes in the RTL code and the flops are well preserved and there is no combi loop anymore within quartus 19.3/arria 10 ;-)

This synthesis keep work for few nodes but not all.

What I just saw in the timing analyzer of quartus 13.1, it does see apparently those combi loops, but it does not details them and it says this:

Low junction temperature is 0 degrees C

High junction temperature is 85 degrees C

TimeQuest Timing Analyzer is analyzing 110 combinational loops as latches.

So in Quartus 13.1 for the stratix 3, quartus cuts the paths

while for Quartus 19.3 and the arria 10, it does not cut the paths and tries to honor the non sense timings,

which leads to super long routing and -20 ns hold tme violations.

Would it be possible to tell Quartus 19.3 to tell him to analyze combi loop as latches like in quartus 13.1?

Maybe with an option in the QSF or so?

BTW, is there a ticketing system at Intel like it was the case during Altera time?

Forums is not giving proper support, we pay for the quartus license,

we expect better support than this!

Hi,

Upon checking, this is the new feature added. The Intel Quartus Prime Pro edition software v19.3 automatically analyzes the correct amount of time borrowing based on arrival time for latches. This is why you see timing analysis on the latches.

Thanks.

Hi,

Please allow me some time to consult engineering team.

Thanks.

Hi,

Kindly provide the information below requested by the engineering team:

There are various INIs that disable various aspects of latch support / borrowing in 19.3. Before recommending anything specific, could you explain exactly why the customer wants to disable latch analysis? What's the design, what is the customer trying to achieve, etc? I want to make sure that our latch support will be in a state that will work for all customers.

Thanks

Any update from Intel side?

Hi,

I am sorry for the delay in response as I was out of office for a week.

I have yet to receive the reply from engineering. I will send a note to the team again.

Thanks.