huge delay inserted by Quartus 19.3 pro on the Arria 10 FPGA

This synthesis keep work for few nodes but not all.

What I just saw in the timing analyzer of quartus 13.1, it does see apparently those combi loops, but it does not details them and it says this:

Low junction temperature is 0 degrees C

High junction temperature is 85 degrees C

TimeQuest Timing Analyzer is analyzing 110 combinational loops as latches.

So in Quartus 13.1 for the stratix 3, quartus cuts the paths

while for Quartus 19.3 and the arria 10, it does not cut the paths and tries to honor the non sense timings,

which leads to super long routing and -20 ns hold tme violations.

Would it be possible to tell Quartus 19.3 to tell him to analyze combi loop as latches like in quartus 13.1?

Maybe with an option in the QSF or so?

BTW, is there a ticketing system at Intel like it was the case during Altera time?

Forums is not giving proper support, we pay for the quartus license,

we expect better support than this!