ContributorHello,
I see a huge delay inserted by Quartus 19.3 pro on the Arria 10 FPGA.
This was not seen in the stratix III FPGA using quartus 13.1.
I will attach the picture showing this.
This lead to huge hold time violations.
Something named ~la_lab/laboutb by Quartus.
I saw another Topic where another person had similar issue with the Arria 10.
How can this be solved?
Regular ContributorHi,
I have sent an email to you to request some information. Please let me know if you did not receive.
Thanks.
ContributorI received it:
"Looking into this further, I don't think this has anything to do with the latch timing analysis changes introduced in 19.3. The customer is upgrading from 13.1 (!) all the way to 19.3 and is changing device families - and most of the complaints relate to how certain structures get synthesized (as a latch, as a comb loop, etc) and how the circuit gets routed (with huge clock skew) - I did not see anything specific about incorrect timing analysis, and "turning off latch analysis" (whatever that may actually mean) is likely the wrong solution here. This case likely has more to do with changes in synthesis, router and/or device architecture from 13.1 all the way to 19.1. To close this case, please provide the following:
(a) a QAR, (b) a full timing report of this path saved to a text file, with show_routing and full details, not just a screenshot, (c) the relevant RTL code snippets,
"
Please note that the exclamation mark after the 13.1 is not relevant as they should know that quartus 13.1 was the only version supprting the familly III of stratix and cyclone.
Talking about the family, stratix 10 on quartus 19.3 shows the same behavior than the arria 10.
The same timing issue also occurs when the netlist comes from synplify pro, so this may be a router issue then , in post v13.1.
I will not provide a project as it is for a chip development, sorry about this.
We will stick to the stratix III/cyclone III platform with quartus 13.1 then.
ContributorAs we eventually have to move to the arria 10, I will try to create a small test case in the future to show the issue,
Regular ContributorHi,
Sure. You may attach a small test case in the future so that I can send the testcase to the team for investigation.
Thanks.
Contributorlooks like Timing analyzer was fixed in 20.1, I will test it:
In certain compilation modes, the Fitter (Finalize) stage takes advantage of time borrowing capability in some of the flip-flops in Intel® Stratix® 10 and Intel® Arria® 10 devices to produce better timing results.
As a result of this optimization, the timing analysis reports might contain line items indicating borrowed time.
If your design contains level-sensitive latches, time borrowed at these latches is not automatically analyzed unless you use the following Timing Analyzer command: update_timing_netlist -dynamic_borrow in the Timing Analyzer.
https://www.intel.com/content/www/us/en/programmable/documentation/ewa1443722509979.html
Can you confirm?
