huge delay inserted by Quartus 19.3 pro on the Arria 10 FPGA

looks like Timing analyzer was fixed in 20.1, I will test it:

In certain compilation modes, the Fitter (Finalize) stage takes advantage of time borrowing capability in some of the flip-flops in Intel® Stratix® 10 and Intel® Arria® 10 devices to produce better timing results.

As a result of this optimization, the timing analysis reports might contain line items indicating borrowed time.

If your design contains level-sensitive latches, time borrowed at these latches is not automatically analyzed unless you use the following Timing Analyzer command: update_timing_netlist -dynamic_borrow in the Timing Analyzer.

https://www.intel.com/content/www/us/en/programmable/documentation/ewa1443722509979.html

Can you confirm?