huge delay inserted by Quartus 19.3 pro on the Arria 10 FPGA

I've been looking in the synthesis log,

and for both the arria10 and stratix 10 quartus synthesis have the intention to turn the Preset/clear register into a latch:

Warning(13310): Register "rfd_ic_i|u_top|u_core|u_atlas|A_flexcomm_array[1].A_flexcomm|A_flexcomm|A_bi2c_gen.A_bi2c_core|timeout_detect_inst|stop_stage2" is converted into an equivalent circuit using register "rfd_ic_i|u_top|u_core|u_atlas|A_flexcomm_array[1].A_flexcomm|A_flexcomm|A_bi2c_gen.A_bi2c_core|timeout_detect_inst|stop_stage2~synth" and latch "rfd_ic_i|u_top|u_core|u_atlas|A_flexcomm_array[1].A_flexcomm|A_flexcomm|A_bi2c_gen.A_bi2c_core|timeout_detect_inst|stop_stage2~synth"

Warning(13310): Register "rfd_ic_i|u_top|u_core|u_atlas|A_flexcomm_array[1].A_flexcomm|A_flexcomm|A_bi2c_gen.A_bi2c_core|slave_inst|pending_i_capture" is converted into an equivalent circuit using register "rfd_ic_i|u_top|u_core|u_atlas|A_flexcomm_array[1].A_flexcomm|A_flexcomm|A_bi2c_gen.A_bi2c_core|slave_inst|pending_i_capture~synth" and latch "rfd_ic_i|u_top|u_core|u_atlas|A_flexcomm_array[1].A_flexcomm|A_flexcomm|A_bi2c_gen.A_bi2c_core|slave_inst|pending_i_capture~synth"

Warning(13004): Presettable and clearable registers converted to equivalent circuits with latches. Registers power-up to an undefined state, and DEVCLRn places the registers in an undefined state.

Warning(13310): Register "rfd_ic_i|u_top|u_core|u_atlas|A_flexcomm_array[1].A_flexcomm|A_flexcomm|A_bi2c_gen.A_bi2c_core|timeout_detect_inst|stop_stage2" is converted into an equivalent circuit using register "rfd_ic_i|u_top|u_core|u_atlas|A_flexcomm_array[1].A_flexcomm|A_flexcomm|A_bi2c_gen.A_bi2c_core|timeout_detect_inst|stop_stage2~synth" and latch "rfd_ic_i|u_top|u_core|u_atlas|A_flexcomm_array[1].A_flexcomm|A_flexcomm|A_bi2c_gen.A_bi2c_core|timeout_detect_inst|stop_stage2~synth"

Warning(13310): Register "rfd_ic_i|u_top|u_core|u_atlas|A_flexcomm_array[1].A_flexcomm|A_flexcomm|A_bi2c_gen.A_bi2c_core|slave_inst|pending_i_capture" is converted into an equivalent circuit using register "rfd_ic_i|u_top|u_core|u_atlas|A_flexcomm_array[1].A_flexcomm|A_flexcomm|A_bi2c_gen.A_bi2c_core|slave_inst|pending_i_capture~synth" and latch "rfd_ic_i|u_top|u_core|u_atlas|A_flexcomm_array[1].A_flexcomm|A_flexcomm|A_bi2c_gen.A_bi2c_core|slave_inst|pending_i_capture~synth"

So I guess the difference between the Stratix 3 and the Arria 10 is that timing analyzer has changed between quartus 13.1 and quartus 19.3 on latches, is it?

There is no report of combinational loop in the Quartus 13.1 when latches are asserted to solve the clear/preset reg by synplify pro (and of course Quartus does not see preset/clear as it has already been converted by Synplify pro).