Contributorhow to link everything together?
Dear Intel Support/Expert,
I am learning how to use Arria 10 SoC Development Kit. and planning to purchase a Kit, but I feel really confused with the way Intel document the design files.
from the web address
Intel Arria 10 SX SoC Development Kit
there is a link Intel Arria 10 SX SoC Package Installer (ES2 Edition), I download the package which is called arria10_10as066n3f40e2sge2_soc_v15.1.2.zip. after I unzip it. there are 3 directories.
1. board_design_files. which I can see it is the board design file, like schematic and PCB board file. this is very clear, I believe I can make a duplicate board from here.
2. document, there is only 1 file called ug_a10_soc_dev_kit.pdf, I believe this is a document teach you how to use the board, but not how to use the FPGA.
3. examples. I find many examples seems is teaching how to use FPGA, for example, in sub directory these is transceiver\prd\bts_pcie\bus_pcie.zip. while I compile this bus_pcie project. I got an error message. as a new bee, don't understand what is this mean and how to solve it.
Error (18757): The old Physical Synthesis has been replaced by the Advanced Physical Synthesis for this device family, but there are still Physical Synthesis assignments in the project's Quartus Settings File (.qsf). Support for the following assignments has been discontinued - "PHYSICAL_SYNTHESIS_COMBO_LOGIC, PHYSICAL_SYNTHESIS_REGISTER_DUPLICATION, PHYSICAL_SYNTHESIS_REGISTER_RETIMING".
I couldn't find in this package any guide or application note, explain that how to use this pcie.zip. and there is not an example project that can generate the top .sof file.
as a new guy try to learn the FPGA, is I missed something here? if not then the development kit will have almost no value to me. I can learn how to load the sof file to the board and run test program. what I really need is an FPGA project example which can show me how to generate this .sof file.
To put my question more straight forward, is there any document that tell me in this develop kit how to integrate the PCIe module with the emif. I notice there is a example like
"PCI Express Gen3 x16 AVMM DMA with DDR4 Memory Reference Design ".
I guess it is a example project which include a PCI, DMA and DDR4 module together. but this is only for Stratix 10. not for the Arria dev board.
Thanks,
David
Hi David,
Regarding the error message, I think this is due to different versions of the Intel Quartus Prime software that you are using and the version used to create the example. Some of the qsf settings in older version are not supported in the newer version.
For reference design, you may find in the link below. User Guides and Reference Designs > Reference design.
Besides the reference design, you may also generate some simple example designs using the IP parameter setting GUI.
Thanks
Best regards,
KhaiY
