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dsun01's avatar
dsun01
Icon for Contributor rankContributor
4 years ago
Solved

how to link everything together?

Dear Intel Support/Expert, I am learning how to use Arria 10 SoC Development Kit. and planning to purchase a Kit, but I feel really confused with the way Intel document the design files. from th...
  • KhaiChein_Y_Intel's avatar
    KhaiChein_Y_Intel
    4 years ago

    Hi David,

    Regarding the error message, I think this is due to different versions of the Intel Quartus Prime software that you are using and the version used to create the example. Some of the qsf settings in older version are not supported in the newer version.

    For reference design, you may find in the link below. User Guides and Reference Designs > Reference design.

    https://www.intel.com/content/www/us/en/programmable/support/support-resources/support-centers/pcie-support.html

    Besides the reference design, you may also generate some simple example designs using the IP parameter setting GUI.

    Thanks

    Best regards,

    KhaiY

KhaiChein_Y_Intel's avatar
KhaiChein_Y_Intel
Icon for Regular Contributor rankRegular Contributor
4 years ago

Hi David,

Regarding the error message, I think this is due to different versions of the Intel Quartus Prime software that you are using and the version used to create the example. Some of the qsf settings in older version are not supported in the newer version.

For reference design, you may find in the link below. User Guides and Reference Designs > Reference design.

https://www.intel.com/content/www/us/en/programmable/support/support-resources/support-centers/pcie-support.html

Besides the reference design, you may also generate some simple example designs using the IP parameter setting GUI.

Thanks

Best regards,

KhaiY

dsun01's avatar
dsun01
Icon for Contributor rankContributor
4 years ago

Hi KhaiY,

After I click Edit the Qsys of the top module, I got the following errors, I think to fully understand this problems, I need to carefully read the emif IP and dma IP user manual, any quick solution.

Error: top.DUT.dma_rd_master/emif_0.ctrl_amm_0: Missing connection start (try "Remove Dangling Connections")
Error: top.DUT.dma_rd_master/DUT.rd_dts_slave: Missing connection start (try "Remove Dangling Connections")
Error: top.DUT.dma_rd_master/DUT.rd_dts_slave: Missing connection end (try "Remove Dangling Connections")
Error: top.DUT.dma_rd_master/DUT.wr_dts_slave: Missing connection start (try "Remove Dangling Connections")
Error: top.DUT.dma_rd_master/DUT.wr_dts_slave: Missing connection end (try "Remove Dangling Connections")
Error: top.DUT.dma_wr_master/mm_clock_crossing_bridge_0.s0: Missing connection start (try "Remove Dangling Connections")
Error: top.DUT.rd_dcm_master/DUT.txs: Missing connection start (try "Remove Dangling Connections")
Error: top.DUT.rd_dcm_master/DUT.txs: Missing connection end (try "Remove Dangling Connections")
Error: top.DUT.rxm_bar4/emif_0.ctrl_amm_0: Missing connection start (try "Remove Dangling Connections")
Error: top.DUT.wr_dcm_master/DUT.txs: Missing connection start (try "Remove Dangling Connections")
Error: top.DUT.wr_dcm_master/DUT.txs: Missing connection end (try "Remove Dangling Connections")
Error: top.DUT.app_nreset_status/clk_0.clk_in_reset: Missing connection start (try "Remove Dangling Connections")
Error: top.DUT.app_nreset_status/emif_0.global_reset_n: Missing connection start (try "Remove Dangling Connections")
Error: top.DUT.app_nreset_status/mm_clock_crossing_bridge_0.s0_reset: Missing connection start (try "Remove Dangling Connections")
Error: top.DUT: DUT.pld_clk must be connected to a clock output
Error: top.DUT.dma_wr_master: Data width must be of power of two and between 8 and 4096

I am just running the example project, why there are still so many errors during loading?

Best,

David