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dsun01's avatar
dsun01
Icon for Contributor rankContributor
5 years ago
Solved

how to link everything together?

Dear Intel Support/Expert, I am learning how to use Arria 10 SoC Development Kit. and planning to purchase a Kit, but I feel really confused with the way Intel document the design files. from th...
  • KhaiChein_Y_Intel's avatar
    KhaiChein_Y_Intel
    5 years ago

    Hi David,

    Regarding the error message, I think this is due to different versions of the Intel Quartus Prime software that you are using and the version used to create the example. Some of the qsf settings in older version are not supported in the newer version.

    For reference design, you may find in the link below. User Guides and Reference Designs > Reference design.

    https://www.intel.com/content/www/us/en/programmable/support/support-resources/support-centers/pcie-support.html

    Besides the reference design, you may also generate some simple example designs using the IP parameter setting GUI.

    Thanks

    Best regards,

    KhaiY

KhaiChein_Y_Intel's avatar
KhaiChein_Y_Intel
Icon for Regular Contributor rankRegular Contributor
5 years ago

Hi David,

Regarding the error message, I think this is due to different versions of the Intel Quartus Prime software that you are using and the version used to create the example. Some of the qsf settings in older version are not supported in the newer version.

For reference design, you may find in the link below. User Guides and Reference Designs > Reference design.

https://www.intel.com/content/www/us/en/programmable/support/support-resources/support-centers/pcie-support.html

Besides the reference design, you may also generate some simple example designs using the IP parameter setting GUI.

Thanks

Best regards,

KhaiY

dsun01's avatar
dsun01
Icon for Contributor rankContributor
5 years ago

Hi KhaiY,

I following your instruction, and download two example project from Intel,

Arria10_PCIeGen3x8_DMA_18_0.par, for Quatrus Pro, I only have a Standard version, so I couldn't use this example.

AN708_q170.par is this also for Pro version. I can open the project, but when I update the IP automatically.

it will have the errors, like this.

Error: set_parameter_value: No parameter sriov2_exprom_en_hwtcl
while executing
"set_parameter_value $name $value"
(procedure "ip_set_parameter_value" line 6)
invoked from within
"ip_set_parameter_value $name $value"
(procedure "ip_set" line 24)
invoked from within
"ip_set "parameter.$name.value" $value"
(procedure "::altera_pcie_a10_hip::parameters::upgrade" line 28)
invoked from within
"::altera_pcie_a10_hip::parameters::upgrade altera_pcie_a10_hip 17.0 {pf2_bar2_size_hwtcl 12 slave_address_map_4_hwtcl 28 pf0_vf_bar2_size_hwtcl 12 pf0..."

I guess it is also for Quartus Pro version, right? if it also works for standard version, then I got the following error message when I Edit the Qsys top.

Thanks,

David

  • dsun01's avatar
    dsun01
    Icon for Contributor rankContributor
    5 years ago

    KyaiY

    Good new is that after I made the following process, the project pass compilation. but I am not sure the modification I made working or not.

    after “remove danling connections" become 4 errors.

    Error: top.DUT: DUT.pld_clk must be connected to a clock output

    connected to clk0.clk

    Error: top.clk_0: clk_0.clk_in_reset must be connected to a reset source

    connected to emif_usr_reset_n

    Error: top.emif_0: emif_0.global_reset_n must be connected to a reset source

    connected to emif_usr_reset_n


    Error: top.mm_clock_crossing_bridge_0: mm_clock_crossing_bridge_0.s0_reset must be connected to a reset source

    connected to emif_usr_reset_n

    regenerate the IP core, pass
    ----------------------------
    commented this line in TOP module.
    // .core_clk_out_clk(core_clkout),

    I am going to see if I can do some simulation. it will take a while.

    Thank you for your help.

    David