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RLee42's avatar
RLee42
Icon for Occasional Contributor rankOccasional Contributor
6 years ago

How can I assign a node is not a clock for TimeQuest

Hi,

​

Quartus TimeQuest infers a PIN as a clock because I need to use it as the way of a clock for some reason. However, it's a not a clock and mostly used as a data in the design.

I couldn't find the "not a clock" assignment, so I tried the steps with a problem as below:

  1. Let's say the PIN name is signal, and I have two signals by using "assign signal_clk = signal;" and "assign signal_data = signal;";
  2. I'd like to use create_clock for signal_clk which is used as the way of a clock only, but I couldn't find the node when I tried to add a node of create_clock in TimeQuest.
  3. Note: There is no flip-flop but only wire between the PIN signal and signal_clk.

My questions are:

  1. Is there any way to let Quartus TimeQuest know it's not a clock?
  2. What's the reason that I couldn't find the node for signal_clk, may because there is no flip-flop that it's regarded as the PIN itself?

Thank you.

Best regards,

Ross

8 Replies

  • IDeyn's avatar
    IDeyn
    Icon for Contributor rankContributor
    6 years ago

    Hi RLee42,

    First of all, your description is very uncertain.

    My answers to your questions are:

    1. There is no way in modern Quartus software to create "not a clock" assignment.
    2. To answer that you'd better attach RTL netlist.

    Hope that helps.

    --

    Best Regards,

    Ivan

    • RLee42's avatar
      RLee42
      Icon for Occasional Contributor rankOccasional Contributor
      6 years ago

      Hi Ivan,

      Thank you for your information.

      Sorry that I didn't describe it clearly.

      For 1, thank you for letting me confirm there is no "not a clock" assignment any more.

      For 2, the net signal_clk and signal_data couldn't be found as they were synthesized away. I could use synthesis attribute to avoid this which solved my issue.

      Here are RTL code I mentioned above, which might be better to show as below:

      ...

      input logic signal;

      ...

      logic signal_clk;

      logic signal_data;

      ...

      assign signal_clk = signal;

      assign signal_data = signal;

      ...

      Cheers,

      Ross

      • IDeyn's avatar
        IDeyn
        Icon for Contributor rankContributor
        6 years ago

        Hi RLee42,

        All right, as I understand you solved your problem. Am I right?

        --

        Best Regards,

        Ivan

  • sstrell's avatar
    sstrell
    Icon for Super Contributor rankSuper Contributor
    6 years ago

    Yeah, I'm not quite sure what you're trying to do here. RTL code or a diagram would help.

    #iwork4intel

    • RLee42's avatar
      RLee42
      Icon for Occasional Contributor rankOccasional Contributor
      6 years ago

      Hi sstrell,

      Thank you for your time and it was solved.

      Cheers,

      Ross

  • GuaBin_N_Intel's avatar
    GuaBin_N_Intel
    Icon for Contributor rankContributor
    6 years ago
    Not really understand what you trying to do but have some inputs to your questions. Is there any way to let Quartus TimeQuest know it's not a clock? No SDC can tell that it's not a clock signal. Once a signal connected to any clock port of FF will be deemed as clock signal in the check rule of TQ. You either ignore it in the report or assign it with clock constraint. What's the reason that I couldn't find the node for signal_clk, may because there is no flip-flop that it's regarded as the PIN itself? Yes, it's likely to be synthesized away since the "PIN" is connected directly to "signal_clk" . Anyhow, you can preserve that signal after post-fit using synthesis attribute https://www.intel.com/content/www/us/en/programmable/quartushelp/17.0/hdl/vlog/vlog_file_dir.htm, perserve
    • RLee42's avatar
      RLee42
      Icon for Occasional Contributor rankOccasional Contributor
      6 years ago

      Hi GNg,

      ​

      Thank you for your help.

      Sorry I didn't make the question clear, however, your information could help solving it.

      It was solved by adding synthesis keep.

      Thank you.​

      Cheers,

      Ross