Forum Discussion
Hi RLee42,
First of all, your description is very uncertain.
My answers to your questions are:
- There is no way in modern Quartus software to create "not a clock" assignment.
- To answer that you'd better attach RTL netlist.
Hope that helps.
--
Best Regards,
Ivan
- RLee427 years ago
Occasional Contributor
Hi Ivan,
Thank you for your information.
Sorry that I didn't describe it clearly.
For 1, thank you for letting me confirm there is no "not a clock" assignment any more.
For 2, the net signal_clk and signal_data couldn't be found as they were synthesized away. I could use synthesis attribute to avoid this which solved my issue.
Here are RTL code I mentioned above, which might be better to show as below:
...
input logic signal;
...
logic signal_clk;
logic signal_data;
...
assign signal_clk = signal;
assign signal_data = signal;
...
Cheers,
Ross
- RLee427 years ago
Occasional Contributor
Hi Ivan,
Yes, it was solved by adding synthesis keep.
Then I could add clock constraint on "signal_clk" instead of "signal" as shown above.
Thank you.
Best Regards,
Ross