Forum Discussion
RLee42
Occasional Contributor
7 years agoHi Ivan,
Thank you for your information.
Sorry that I didn't describe it clearly.
For 1, thank you for letting me confirm there is no "not a clock" assignment any more.
For 2, the net signal_clk and signal_data couldn't be found as they were synthesized away. I could use synthesis attribute to avoid this which solved my issue.
Here are RTL code I mentioned above, which might be better to show as below:
...
input logic signal;
...
logic signal_clk;
logic signal_data;
...
assign signal_clk = signal;
assign signal_data = signal;
...
Cheers,
Ross