Forum Discussion
GuaBin_N_Intel
Contributor
7 years agoNot really understand what you trying to do but have some inputs to your questions.
Is there any way to let Quartus TimeQuest know it's not a clock?
No SDC can tell that it's not a clock signal. Once a signal connected to any clock port of FF will be deemed as clock signal in the check rule of TQ. You either ignore it in the report or assign it with clock constraint.
What's the reason that I couldn't find the node for signal_clk, may because there is no flip-flop that it's regarded as the PIN itself?
Yes, it's likely to be synthesized away since the "PIN" is connected directly to "signal_clk" . Anyhow, you can preserve that signal after post-fit using synthesis attribute https://www.intel.com/content/www/us/en/programmable/quartushelp/17.0/hdl/vlog/vlog_file_dir.htm, perserve
RLee42
Occasional Contributor
7 years agoHi GNg,
Thank you for your help.
Sorry I didn't make the question clear, however, your information could help solving it.
It was solved by adding synthesis keep.
Thank you.
Cheers,
Ross