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Sameer-sahu's avatar
Sameer-sahu
Icon for Occasional Contributor rankOccasional Contributor
2 years ago

Hierarchy not found in Modelsim during RTL simulation

I am using Quartous prime 19.1 standard edition. I have a hierarchical design (comprising verilog file), see screenshot (some names hidden).

When I launch RTL Simulation from Quartus, I see that in Modelsim the same project hierarchy do not exist.

Therefore, I am not able to view the internal signals of sub modules in the wave window. How can I retain the hierarchy in modelsim to view the internal signals?

Thanks & Regards

Sameer

Board Debug
Fpga Devkit

2 Replies

  • SyafieqS's avatar
    SyafieqS
    Icon for Super Contributor rankSuper Contributor
    2 years ago

    Seem to me your signals are being optimized away by Modelsim.

    Can you try to preserve them?

    Use +acc with vopt to preserve visibility of all objects in the design or vsim -voptargs with +acc for selective design object visibility during debugging.

    Let me know any update


  • SyafieqS's avatar
    SyafieqS
    Icon for Super Contributor rankSuper Contributor
    2 years ago

    As we do not receive any response from you on the previous question/reply/answer that we have provided. Please login to https://supporttickets.intel.com/, view details of the desire request, and post a feed/response within the next 15 days to allow me to continue to support you. After 15 days, this thread will be transitioned to community support. The community users will be able to help you on your follow-up questions.


    p/s: If any answer from community or Intel support are helpful, please feel free to mark as solution, give Kudos and rate 5/5 survey