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Sameer-sahu's avatar
Sameer-sahu
Icon for Occasional Contributor rankOccasional Contributor
3 years ago

Hierarchy not found in Modelsim during RTL simulation

I am using Quartous prime 19.1 standard edition. I have a hierarchical design (comprising verilog file), see screenshot (some names hidden). When I launch RTL Simulation from Quartus, I see that...
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SyafieqS's avatar
SyafieqS
Icon for Super Contributor rankSuper Contributor
3 years ago

Seem to me your signals are being optimized away by Modelsim.

Can you try to preserve them?

Use +acc with vopt to preserve visibility of all objects in the design or vsim -voptargs with +acc for selective design object visibility during debugging.

Let me know any update