Forum Discussion
Sameer-sahu
Occasional Contributor
3 years agoHierarchy not found in Modelsim during RTL simulation
I am using Quartous prime 19.1 standard edition. I have a hierarchical design (comprising verilog file), see screenshot (some names hidden). When I launch RTL Simulation from Quartus, I see that...
SyafieqS
Super Contributor
3 years agoAs we do not receive any response from you on the previous question/reply/answer that we have provided. Please login to https://supporttickets.intel.com/, view details of the desire request, and post a feed/response within the next 15 days to allow me to continue to support you. After 15 days, this thread will be transitioned to community support. The community users will be able to help you on your follow-up questions.
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