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dsun01's avatar
dsun01
Icon for Contributor rankContributor
3 years ago
Solved

Fitter error of PCIe in A10 GX dev board

Dear Intel Support/Expert

I have a project with 16 lanes of JESD, before I integrate PCIe, it could be compiled successfully.

after I added in PCIe( Avalon-MM with DMA, Gen3X8, Interface:256bit, 250MHz). it failed while fitting,

Error(14566): The Fitter cannot place 1 periphery component(s) due to conflicts with existing constraints (1 HSSI_PMA_TX_BUF(s)). Fix the errors described in the submessages, and then rerun the Fitter. The Intel FPGA Knowledge Database may also contain articles with information on how to resolve this periphery placement failure. Review the errors and then visit the Knowledge Database at https://www.altera.com/support/support-resources/knowledge-base/search.html and search for this specific error message number.
Error(175001): The Fitter cannot place 1 HSSI_PMA_TX_BUF, which is within Intel Arria 10/Cyclone 10 Hard IP for PCI Express jesd204b_pcie_a10_hip_0_altera_pcie_a10_hip_2011_ubtnd7a.
Error(16234): No legal location could be found out of 72 considered location(s). Reasons why each location could not be used are summarized below:
Error(175006): There is no routing connectivity between the HSSI_PMA_TX_BUF and destination HSSI_RX_PCS_PMA_INTERFACE
Error(175022): The HSSI_PMA_TX_BUF could not be placed in any location to satisfy its connectivity requirements
Error(20196): Location(s) already occupied and the components cannot be merged. (8 locations affected)

I hope the chip has enough resources to hold both modules. I don't know how to manipulate the design to make the fitting pass.

Is there general procedure to tracing this kind of "no routing connectivity"?

I can provide the design if anyone want have a look.

thank you very much.

David

10 Replies

  • Wincent_Altera's avatar
    Wincent_Altera
    Icon for Regular Contributor rankRegular Contributor
    3 years ago

    Hi David,


    Thanks for reaching. there is an same error reported before.

    For Error 14566 , you can try use the following assignment. set_global_assignment -name AUTO_RESERVE_CLKUSR_FOR_CALIBRATION OFF

    Detail information you may get in the KDB https://www.intel.com/content/www/us/en/support/programmable/articles/000074695.html#:~:text=%C2%AE%2010%20devices%3A-,Error%20(14566)%3A%20The%20Fitter%20cannot%20place%201%20periphery%20component,and%20then%20rerun%20the%20Fitter.


    Please try it and let me know the finding,

    Regards,

    Wincent_Intel




    • dsun01's avatar
      dsun01
      Icon for Contributor rankContributor
      3 years ago

      Hi Wincent

      Thank you for your prompt response, I tried it, it didn't work.

      I searched the error database; I found this link is the closest one

      Error (175001): The Fitter cannot place 1 HSSI_PMA_TX_CGB, which is... (intel.com)

      Description

      You may see this error when using the Arria® 10 device, Native PHY IP in PIPE mode. This is error is due to a mismatch between bonding master setting and physical transceiver channel placement.

      Resolution

      To fix this problem modify the bonding master setting in Native PHY IP to match transceiver channel placement. The bonding master should be in physical channel CH1 or CH4. For example, if the following x4 PIPE transceiver channel placement is used, the bonding master is 1.

      Logical Channel
      		 Physical Channel
      Ch0 GXBL1C_RX_CH3
      Ch1 GXBL1C_RX_CH4
      Ch2 GXBL1C_RX_CH5
      Ch3 GXBL1D_RX_CH0

      but I don't fully understand what the Description and Resolution is talking about.

      could you please give me more detail of the resolution. I am not very familiar with PCIe IP, I instruction how to operate.

      Thank you again.

      David

      • Wincent_Altera's avatar
        Wincent_Altera
        Icon for Regular Contributor rankRegular Contributor
        3 years ago

        Hi David,

        The KDB provided is for Tranceiver PHY IP (Native PHY IP) , not so related to PCIe. Not sure if you had include it in your design or not.
        If have, you can set it as below picture, via the PHY IP GUI.

        Each of our HardIPs has a dedicated perstn pin location.
        PCIe IP need to assign to fix channel location, detail about the IP location you may refer to Arria 10 User Guide)
        Please check and ensure that you assign correctly.

        Hope this is helpful.
        Regards,
        Wincent_Intel

  • Wincent_Altera's avatar
    Wincent_Altera
    Icon for Regular Contributor rankRegular Contributor
    3 years ago

    Hi David,


    Is there any new error message ? after the assigned ?

    If yes appreciate if you can share with me.


    • dsun01's avatar
      dsun01
      Icon for Contributor rankContributor
      3 years ago

      Hi wchiah

      I guess the problem was because a typo of the highspeed pin name. after I corrected it, there is no error message anymore.

      thank you for all the support

      David

      • Wincent_Altera's avatar
        Wincent_Altera
        Icon for Regular Contributor rankRegular Contributor
        3 years ago

        Hi David,

        Glad that your problem solve, Nice to work with you.
        Feel free to create a new case if you face any problems in future.
        If the case is assigned to me again, I am happy to continue working with you.

        If you feel your support experience was less than a 9 or 10,

        please allow me to correct it before closing or please let me know the cause so that I may improve your future support experience.

        Regards,

        Wincent_Intel