Fitter error of PCIe in A10 GX dev board

Hi David,

KDB means Knowledge Base, It is the link provided by you

• Error (175001): The Fitter cannot place 1 HSSI_PMA_TX_CGB, which is... (intel.com)
• As mention it is more related to Native PHY IP (tranceiver), which might not be the error to your problem as you are using standard PCIe design.

Step how to Assigning Pin I/O Standards in the Intel® Quartus® Prime Pin Planner you may refer to the link.

For the correct Pin number, you may refer to the user guide below under Table 5-16 , page 72/103

https://www.intel.com/content/dam/support/us/en/programmable/support-resources/bulk-container/support/boards-kits/arria10/fpga/a10-fpga-dk-ug.pdf

Hope this is helpful, let me know if further clarification is needed.

Regards,

Wincent_Intel