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dsun01's avatar
dsun01
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3 years ago
Solved

Fitter error of PCIe in A10 GX dev board

Dear Intel Support/Expert I have a project with 16 lanes of JESD, before I integrate PCIe, it could be compiled successfully. after I added in PCIe( Avalon-MM with DMA, Gen3X8, Interface:256bit...
Wincent_Altera's avatar
Wincent_Altera
Icon for Regular Contributor rankRegular Contributor
3 years ago

Hi David,


Thanks for reaching. there is an same error reported before.

For Error 14566 , you can try use the following assignment. set_global_assignment -name AUTO_RESERVE_CLKUSR_FOR_CALIBRATION OFF

Detail information you may get in the KDB https://www.intel.com/content/www/us/en/support/programmable/articles/000074695.html#:~:text=%C2%AE%2010%20devices%3A-,Error%20(14566)%3A%20The%20Fitter%20cannot%20place%201%20periphery%20component,and%20then%20rerun%20the%20Fitter.


Please try it and let me know the finding,

Regards,

Wincent_Intel




dsun01's avatar
dsun01
Icon for Contributor rankContributor
3 years ago

Hi Wincent

Thank you for your prompt response, I tried it, it didn't work.

I searched the error database; I found this link is the closest one

Error (175001): The Fitter cannot place 1 HSSI_PMA_TX_CGB, which is... (intel.com)

Description

You may see this error when using the Arria® 10 device, Native PHY IP in PIPE mode. This is error is due to a mismatch between bonding master setting and physical transceiver channel placement.

Resolution

To fix this problem modify the bonding master setting in Native PHY IP to match transceiver channel placement. The bonding master should be in physical channel CH1 or CH4. For example, if the following x4 PIPE transceiver channel placement is used, the bonding master is 1.

Logical Channel
 Physical Channel
Ch0 GXBL1C_RX_CH3
Ch1 GXBL1C_RX_CH4
Ch2 GXBL1C_RX_CH5
Ch3 GXBL1D_RX_CH0

but I don't fully understand what the Description and Resolution is talking about.

could you please give me more detail of the resolution. I am not very familiar with PCIe IP, I instruction how to operate.

Thank you again.

David

  • Wincent_Altera's avatar
    Wincent_Altera
    Icon for Regular Contributor rankRegular Contributor
    3 years ago

    Hi David,

    The KDB provided is for Tranceiver PHY IP (Native PHY IP) , not so related to PCIe. Not sure if you had include it in your design or not.
    If have, you can set it as below picture, via the PHY IP GUI.

    Each of our HardIPs has a dedicated perstn pin location.
    PCIe IP need to assign to fix channel location, detail about the IP location you may refer to Arria 10 User Guide)
    Please check and ensure that you assign correctly.

    Hope this is helpful.
    Regards,
    Wincent_Intel

    • dsun01's avatar
      dsun01
      Icon for Contributor rankContributor
      3 years ago

      Hi Wincent,

      What is KDB stand for? how to include it in my design?

      I am using standard Intel PCIe IP, here is the parameter setup interface. I couldn't see where I can setup bonding master.

      I choose the parameters and generate example first, it compiled without any problem, after I intergrate to my design, the error happens. I guess there may be a resource conflict. so the assignment is the key point to solve the problem.

      I also attached the QSF file of the example, it doesn't help if I copied all lines into my final project qsf file.

      while I am checking how to assign the channel location. could you please give me a example of the .qsf with the channel location lock. it will make my learning process faster.

      I am an old engineer, still need to learn new skill. Appreciate your help and patience.

      Happy holiday.

      .

      David