Fast & Large block data transfer over USB - DE1/DE2 ?

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The crucial commection for the reset is from the FT2232H pin 46 : BDBUS7, again labled Data3.

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If the FT2232H is being used to configure the Cyclone using passive serial communications with a 1-bit data width, then DATA[0] is the programming signal, and DATA[7:1] are available as control signals.

If the FT2232H is being used to program the Cyclone using Fast passive parallel (FPP), then all DATA[7:0] bits are used during programming.

Once the FPGA enters user-mode, the DATA pins can be configured as user-I/O. If this is the case in the Morph-IC-II, then the 8-bit bus from the FT2232 is a user-bus once the device is configured.

Post the schematic and I'll look.

Cheers,

Dave

OK thanks, Morphic II Schematic attached.

One of the thing I am not clear about, is how to use the ftdi command ft_setbitmode.

It is not clear as to if 1 represents input or output, and I am not clear what I do about bi-directional lines.

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Morphic II Schematic attached.

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DATA3 is just a data connection between the FT2232 and the FPGA. The FPGA can be configured to use it as a DEV_CLR signal, which is basically a reset, without actually having a reset in your top-level design entity. Personally, I'd configure the pin to be a general purpose I/O and treat it as an external reset control in the design.

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One of the thing I am not clear about, is how to use the ftdi command ft_setbitmode.

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Set bitmode is used to change between MPSSE and regular modes.

Check out the attached programmer for the Morph-IC.

Cheers,

Dave

Thanks indeed, reading through it .... see where bit 7 is used as nReset.

Also just trying to use the USB Blaster to do a SignalTap analysis of my design in the Morphic II. First time I have had a USB Blaster to be able to do this. Could be very useful ....

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Thanks indeed, reading through it .... see where bit 7 is used as nReset.

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Right, that is what I wanted you to understand. However, there's two ways this signal can act as reset; it can be configured as DEV_CLRn in your Quartus project setting, and it will keep your design in reset if its held low, or you can configure it as a rstN input to your top-level design, and choose to ignore it or use it.

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Also just trying to use the USB Blaster to do a SignalTap analysis of my design in the Morphic II. First time I have had a USB Blaster to be able to do this. Could be very useful ....

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SignalTapII is extremely useful. Learn to use it. Also learn to use Modelsim.

Cheers,

Dave

On the Morphic II the default reset seems to be a positive logic reset, I have to invert it as the logic I am importing my code from, an EZC1USB module, was a negative logic reset.

-- nRESET: in std_logic; -- FPGA reset, negative on-board reset, EZC1USB

HW_RESET: in std_logic; -- FPGA reset, positive on-board reset, Morphic II

begin

nRESET <= not HW_RESET;

So indeed I can ignore it if I choose - never thought of that - though I do use it extensively to reset things before they run.

How are your further thoughts on using the USB Blaster for data I/O coming on ?

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On the Morphic II the default reset seems to be a positive logic reset, I have to invert it as the logic I am importing my code from, an EZC1USB module, was a negative logic reset.

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Its just a pin, so its up to you to decide what it means :)

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So indeed I can ignore it if I choose - never thought of that - though I do use it extensively to reset things before they run.

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I just meant ignore it while debugging. Resets are generally good to use. However, you should run them through a dual-DFF synchronizer prior to use, so that the synchronized reset deasserts synchronously.

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How are your further thoughts on using the USB Blaster for data I/O coming on ?

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I haven't had a chance to work on it. I've been working on some TimeQuest timing analysis.

Cheers,

Dave

Large & fast USB data transfer - well I have got no further with the DE0 and DE1 interfaces, but thought you might like to see what I have been up to using the MorphicII fpga module - see these two YouTube videos :

http://www.youtube.com/user/labtoolsinstruments

I have a new transient capture/averager module just back from assembly and under test ...

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thought you might like to see what I have been up to using the MorphicII fpga module - see these two YouTube videos :

http://www.youtube.com/user/labtoolsinstruments

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Cool, thanks for sharing.

I watched the Morph-IC-II video, but you didn't say anything about the actual transfer rates though.

What does SignalTap II show in the FPGA fabric? Are all samples showing up over the USB bus into the FTDI FIFOs in a single-shot?

Here's a tutorial on using the USB-Blaster directly. Its slower, since it only has a serial connection to the FPGA, but it should be pretty easy to modify for use on the DE0 and DE1.

http://www.alterawiki.com/wiki/using_the_usb-blaster_as_an_sopc/qsys_avalon-mm_master_tutorial

Cheers,

Dave