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The crucial commection for the reset is from the FT2232H pin 46 : BDBUS7, again labled Data3.
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If the FT2232H is being used to configure the Cyclone using passive serial communications with a 1-bit data width, then DATA[0] is the programming signal, and DATA[7:1] are available as control signals.
If the FT2232H is being used to program the Cyclone using Fast passive parallel (FPP), then all DATA[7:0] bits are used during programming.
Once the FPGA enters user-mode, the DATA pins can be configured as user-I/O. If this is the case in the Morph-IC-II, then the 8-bit bus from the FT2232 is a user-bus once the device is configured.
Post the schematic and I'll look.
Cheers,
Dave
Honored Contributor
