Failed to get MAX10 Triple Speed Ethernet example design to compile

Greetings Altera Experts,

I have been trying to recreate an ALTER example design for a MAX 10 Development kit ::

"MAX 10 Single-Port Triple Speed Ethernet and On-Board PHY Chip Design Example User Guide"

The problem is that when i read in the max10tse_q_18_0_std.par into a new  Quartus project using the same version of Quartus in which the project was originally created from (QUARTUS STD 18.0) it seems to go through initial enumerate and synthesis part OK but then when i try to open the QSYS Platform i see a load of RED errors due to missing components, which are these IP's:
 

st_mux_2_to_1,  aso_splitter,  error_adapter2,  eth_gen, eth_mon

So basically most of the QSYS design apart from the TSE and a reset and clock are missing !

I tried to doing the 'upgrade IP' in Quartus for the Qsys component but that didn't help, and also i did a IP library refresh. Again no help.

Does anybody got any suggestions please as to how to get these missing IP components ? Or is there a Git rep somewhere with a complete design i can compile for a MAX10 dev board using the Triple Speed Ethernet core ? I have attached the Altera User Guide for this example design to this case. I also added a screenshot showing the errors i get from loading up QSYS.

Thanks for any help,

Dr Barry H