alexislms
Contributor
ContributorExample design: Agilex I-series devkit: intel_pcie_pio_1024 not converting TLP to Avalon-MM
Using Quartus Pro 22.1, I followed UG-20330 to generate from scratch the example design of the Agilex I-series Development Kit (ES).
1. Compiling, inserting the driver, the board is correctly recognized.
2. Compiling the user/example intel_fpga_pcie_link_test application
3. Running Automatic detection and 0: Link test - 100 writes and reads
********************************************************* Intel FPGA PCIe Link Test Version 2.0 0: Automatically select a device 1: Manually select a device ********************************************************* > 0 Opened a handle to BAR 0 of a device with BDF 0x100 ********************************************************* 0: Link test - 100 writes and reads 1: Write memory space 2: Read memory space 3: Write configuration space 4: Read configuration space 5: Change BAR for PIO 6: Change device 7: Enable SRIOV 8: Do a link test for every enabled virtual function belonging to the current device 9: Perform DMA 10: Quit program *********************************************************
I can see the TLP arriving in the FPGA but there is no Avalon-MM generated by the obscure intel_pcie_pio_1024 Intel IP core. Therefore the test fails.
And nothing for all the 1024clocks.
Best regards,
