Forum Discussion

alexislms's avatar
alexislms
Icon for Contributor rankContributor
3 years ago

Example design: Agilex I-series devkit: intel_pcie_pio_1024 not converting TLP to Avalon-MM

Using Quartus Pro 22.1, I followed UG-20330 to generate from scratch the example design of the Agilex I-series Development Kit (ES). 1. Compiling, inserting the driver, the board is correctly re...
Wincent_Altera's avatar
Wincent_Altera
Icon for Regular Contributor rankRegular Contributor
3 years ago

Hi,


Thanks for sharing with me your finding.

As investigated, the error can be due to a myriad of reasons and might be difficult to pinpoint exactly.

However, I've laid out some suggestions to help us narrow this down and further confirm the root cause.



Let me know if you have any different thoughts. Hoping to hear back from you.

Regards,

Wincent_C_Intel


  • alexislms's avatar
    alexislms
    Icon for Contributor rankContributor
    3 years ago

    @Wincent_Altera,

    Please read again my first message.

    1. I'm following the example design ug-20330 I mentioned, it's the same link.

    2. As said, the simulation doesn't work.

    Please confirm 1. and 2. work on your side. It isn't working for me and @TBalu (the link in my 2nd message).

    If you don't see any issue on your side, please provide the Quartus Pro 22.1 archive project of the example design that works (hw + sim).

    Regards,

    • Wincent_Altera's avatar
      Wincent_Altera
      Icon for Regular Contributor rankRegular Contributor
      3 years ago

      Hi,

      I do a quick check on the link in your 2nd message.
      It is running simulation in Modelsim, are you getting the same error as well if running in Modelsim ?

      For your case, I don't see any things assign in the PIO_address.

      If you want to read/write from the FPGA via PCIe to talk to another PCIe device my suggestion is as below

      • Use the host PC to determine the PCIe address of the device you need to talk to.
      • Configure the Qsys PCIe address remap registers so that it maps to the region of the device you want to control.
      • Issue a read/write to the Avalon-MM slave interface of the Qsys PCIe component. That Avalon-MM transaction will map to a PCIe transaction that will then perform a read/write to the PCIe device.

      Let me know if you have any other thoughts.

      Regards,

      Wincent_C_Intel

      • alexislms's avatar
        alexislms
        Icon for Contributor rankContributor
        3 years ago

        Hello@Wincent_Altera,

        I tried again with Questa provided with Quartus Pro 22.1 and I still see the error.

        In the other forum topic, @TBalu used Modelsim Intel FPGA Starter Edition 2021.1 and it didn't work.

        Please provide the archive of the project whose the simulation works.

        I see the address in the header (32'h9400_0000) and this base address is correct for the BAR0.

        I am not trying to debug the Intel's example design, I'm just reporting it isn't working when following both user guides.

        The reason I tried to use the example design is to have a project that works out of the box with all the correct parameters.

        Again, if it's working on your side, please provide the archive of the project.

        Regards,