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alexislms
Contributor
ContributorExample design: Agilex I-series devkit: intel_pcie_pio_1024 not converting TLP to Avalon-MM
Using Quartus Pro 22.1, I followed UG-20330 to generate from scratch the example design of the Agilex I-series Development Kit (ES).
1. Compiling, inserting the driver, the board is correctly re...
alexislmsContributor
ContributorAnd I am unable to simulate the design since there is an error that hasn't been answered for 1year: https://community.intel.com/t5/FPGA-Intellectual-Property/Agilex-FPGA-PCIe-Gen5-Example-Design-Simulation-Error/m-p/1328057#M24967
('rtile_s20_v0' file missing)
