E-Tile not working with custom pattern ?

It did set those bits. I am also now able to get a zero bit error. Though If I capture the data via the PMA register they do not fit my pattern at all. How exactly is this data captured ?

I looked further into it and found that there is quite a big skew :

-90.758 u0|etile|xcvr_native_s10_etile_0|g_pma_rsfec_reset.g_auto_reset.reset_ip_auto_etile_inst|reset_control_inst|g_rx.g_rx[0].g_rx.counter_rx_ready|r_reset u0|qsys_rx_snapshot_fifo|qsys_rx_snapshot_fifo|dcfifo_component|auto_generated|fifo_altera_syncram|altera_syncram_impl1|ram_block2a0~reg0 ALTERA_INSERTED_INTOSC_FOR_TRS|divided_osc_clk u0|etile|xcvr_native_s10_etile_0|rx_clkout|ch0 1.600 -90.864 1.384 Slow 900mV 100C Model

Could this be the cause of this problem ?

I have taken another look and just want to summarize a few things:

1. The physical connection seems to work. PRBS31 works when used in the System Console and reaches BER of 0. I also tested to Inject Errors to verify the link is properly working

2. I have taken waveforms with the oscilloscope [image.png] to verify a proper transmission of the data. The 80-bit sequence here was [0x00AAAAAfff0000AAFF5500FFAAAAA000055FFAA]

- I have used two ways to send this data. 1. via the debug interface of the e-tile and also via my own implementation of tx_parallel_data. Both ways worked

3. I have changed the program so that no direct timing violation is recognized by the Quartus Timing Analayzer

4. I used a tcl script inside of the system console. There I was able to get a partial success. I send the sequence [0x1BC,0x2BC,0x3BC,0x4BC,0x5BC,0x6BC,0x7BC,0x8BC] and received [0x2BC,0x3BC, 0x3BC,0xBC,0x1BC,0x2BC,0x3BC,0xBC,0x1BC]

-> The mentioned data was read out by using following commands:

rcfg_etile $phy $channel 0x0001C 0x0 1
rcfg_etile $phy $channel 0x00018 0x4 1
rcfg_etile $phy $channel 0x0001A 0x0 1
rcfg_etile $phy $channel 0x0001A 0x0  1
rcfg_etile $phy $channel 0x0001A 0x0  1
rcfg_etile $phy $channel 0x0001A 0x0  1
rcfg_etile $phy $channel 0x0001A 0x0  1
rcfg_etile $phy $channel 0x0001A 0x0  1
rcfg_etile $phy $channel 0x0001A 0x0 1
rcfg_etile $phy $channel 0x0001A 0x0  1

5. I have added an EYE diagram measured by the System Console Toolkit

=> The general transmission seems to work more or less fine so far. The link should work.

Now the problem begins when I try to read it out via the FPGA Core Interface. I am using a FIFO which writes on rx_ready true and is then readout later. I also verified that the FIFOs are read out properly. I also tried using the Signal Tap Logic Analyzer to read out the data from rx_parallel_data (see attached image). But the receiving data seems completely random. I would assume there is some problem between the PMA and my FPGA core but I can't so where and I am also not sure how to properly debug this part.

I have already tried:

1. Enabling Deskew and adding the deskew bits

2. Reducing the transmission speed

3. Use TX channel bonding

4. Different reference clocks

But nothing has produced a useable result so far. I would be happy about any recommendation on how to proceed.